SR LATCH

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arvind

Joined Nov 4, 2004
18
HI, :) :) :D :D :rolleyes: :rolleyes:
i want to kow what happens in the following situation:
consider a sr latch we know that it undergoes latch when inputs are 0
when inputs are both logic1 we have both outputs Q and Q' equal to 0 which is an invalid state coz Q' and Q are complementary. now if i change both inputs to 0 simultaneously, what will be the output.
:blink: :blink:
 

beenthere

Joined Apr 20, 2004
15,819
Hi,

S-R latches are designed to debounce mechanical switches. It's possible for both inputs to be high simultaneously, but never for them to both be low - at least with a proper design. With a NAND gate S-R latch, both inputs low should make both outputs high.
 
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