HI,
i want to kow what happens in the following situation:
consider a sr latch we know that it undergoes latch when inputs are 0
when inputs are both logic1 we have both outputs Q and Q' equal to 0 which is an invalid state coz Q' and Q are complementary. now if i change both inputs to 0 simultaneously, what will be the output.
:blink: :blink:
i want to kow what happens in the following situation:
consider a sr latch we know that it undergoes latch when inputs are 0
when inputs are both logic1 we have both outputs Q and Q' equal to 0 which is an invalid state coz Q' and Q are complementary. now if i change both inputs to 0 simultaneously, what will be the output.
:blink: :blink: