SR latch initial output

Discussion in 'Digital Circuit Design' started by ewr, Oct 2, 2016.

  1. ewr

    Thread Starter New Member

    Oct 2, 2016
    2
    0
    With NOR SR latch, I don't understand how the gates can output a signal initially. You need two input signals for the NOR gate but initially there is only one input for each of the NOR gate (R and S) since the Q and NOT Q outputs are not generated yet. Can NOR gates output a signal given only one input signal?

    Thank you.

    [​IMG]
     
  2. Papabravo

    Expert

    Feb 24, 2006
    10,144
    1,791
    It depends on the technology used to fabricate the gates and what logic thresholds apply as the gates are powered on. My default assumption is the latch will come up in an indeterminate state as power is applied. At some point the latch should be initialized by activating either the S input or the R input. What you must avoid at all costs is allowing bot R and S to be high (one) at the same time.
     
  3. crutschow

    Expert

    Mar 14, 2008
    13,014
    3,234
    "At all costs" sounds a little ominous. :eek:
    All that will happen if both R and S are high at the same time is that both outputs will be low.
     
  4. dl324

    Distinguished Member

    Mar 30, 2015
    3,244
    621
    In your drawing, both NOR gates have 2 inputs.
     
  5. ewr

    Thread Starter New Member

    Oct 2, 2016
    2
    0
    Yes in the drawing both NOR gates have 2 inputs. But what I don't understand is how the input is generated if it is the output of the other NOR gate. You supply the R input to one NOR gate and S input to the other NOR gate. The other input is the output of the other NOR gate. How does this input generated in the first place since Q and NOT Q output don't exist yet?

    Is it something to do with how the NOR gate is implemented with transistors?
     
  6. AnalogKid

    Distinguished Member

    Aug 1, 2013
    4,539
    1,251
    Assuming that neither the S nor R inputs are floating, then there are three possible cases.
    1. Both inputs are low, the rest condition. The outputs assume complimentary states based on random noise during power up.
    2. One of them is low and the other is high. Whichever input is high forces its gate's output low (no matter what its transient condition might have been during the gate's propagation time), and that sets the conditions for the other gate.
    3. Both inputs are high. Both outputs are low. One output will change when its input goes low.

    ak
     
  7. Papabravo

    Expert

    Feb 24, 2006
    10,144
    1,791
    Which may cause downstream circuits to malfunction. Ominous is relative to the universe you inhabit.
     
Loading...