Spreading spectrum in WCDMA

Discussion in 'Embedded Systems and Microcontrollers' started by romaprince, Dec 19, 2006.

  1. romaprince

    Thread Starter New Member

    Dec 19, 2006
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    Hi, everyone.

    I am a third-year student specialise in Digital Design. I have a project, not suggested by my intructors, in which i want to use FPGAs to spread spectrum of WCDMA system.

    Is there anyone here in this forum who experienced or also like this topics.Please share with me.

    Trung Mai Van
     
  2. Dave

    Retired Moderator

    Nov 17, 2003
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    Hi and Welcome to AAC,

    There are quite a few people on this forum with experience with FPGAs and the general use of embedded systems, however you may not find someone who has specific experience with Wideband Code Divisional Multiplexing Access.

    Are you looking for general information with regards to FPGAs or do you have a specific query with a WCDMA system you are currently working on?

    I'll move this to the Embedded Systems forum since it is a general topic. If you want assistance with a specific project/problem then please post a new thread in The Projects Forum.

    Dave
     
  3. romaprince

    Thread Starter New Member

    Dec 19, 2006
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    Firstly, thank you for your moving my topic into its approciate place in this forum.

    I like both to learn FPGAs generally and finding more information about my project.Unfortunately, as you posted, no member has specific experience with WCDMA.
     
  4. Dave

    Retired Moderator

    Nov 17, 2003
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    Do you have a FPGA of choice? (i.e. one that you will be working with on this project?).

    Dave
     
  5. romaprince

    Thread Starter New Member

    Dec 19, 2006
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    Yeah, i will use Spartan family from Xilinx.But i think that it's not the main problem that can influence my project.

    You're the person who wrote all this tutorial.It's admirable.Because in my country contexts are all written in a not detailed manner.

    Could you give me your contact, such as your yahoo messenger ID if you don't mind?

    Trung Mai Van
     
  6. Dave

    Retired Moderator

    Nov 17, 2003
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    The Spartan family is very popular and there are many resources on the net which would be of use in any project you are undertaking. The widespread use of this device should mean that there are many who could help or even contribute code to your project.

    I would love to take credit for this book, but that would be wrong of me. The original text was written by Tony Kuphaldt (who has since left the project) and has been developed and added to by many over the years. The current coordinator is Dennis Crunkilton who is a regular here at AAC.

    I'm afraid I don't use IM, the only way I can be contacted is through these forums, and via PM or e-mail. I prefer if you have a question that you use the forums here so that others may benefit from the discussion and contribute there insight which is more often than not beyond the help and advice I could give. Also my time can often be restricted so dealing with requests on an individual basis is not something I try to get into, particularly in light of the number of PMs and e-mails I get through this forum.

    Dave
     
  7. romaprince

    Thread Starter New Member

    Dec 19, 2006
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    Okie. I also like to use this forum to discuss on my projects and others'.

    Which HDL that most of members prefer ? VHDL or Verilog.
     
  8. Dave

    Retired Moderator

    Nov 17, 2003
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    Personally, I prefer VHDL because that is the language my digital systems courses at University were focused around, hence I did a lot during my degree and thereafter. I regret never look into Verilog, even just to give me more options. Perhaps one day I'll get the urge to look at Verilog.

    If you are interested in VHDL, I commonly recommend the VHDL Cookbook as a reference source for both beginners and those looking for a VHDL-recap. Have a look.

    Dave
     
  9. romaprince

    Thread Starter New Member

    Dec 19, 2006
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    You're living in UK so it's easy to understand why you used VHDL for your projects.Verilog is prefered in USA and Japan.

    But it doesn't matter which language one is using for their projects.Thanks for your recommended ebook.It's enough for my study now.

    Trung Mai Van.
     
  10. n9352527

    AAC Fanatic!

    Oct 14, 2005
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    Actually, I live in the UK too but I am more used to Verilog than VHDL. The reason is because a long time ago, Verilog had several advantages over early version VHDL. So early adopters and projects, especially geared towards ASICs or IC designs, kind of veered towards Verilog by necessity.

    Subsequent version of VHDL addressed these shortcomings and nowadays they are considered similar in features. But for people like me, it is just more convenient to chug along with what I am comfortable with, hence the preference to Verilog. Although universities do prefer VHDL from early on in the UK, like Dave mentioned. I guess that showed the disparity between educational institutions and what the industries needed at that time :D
     
  11. Dave

    Retired Moderator

    Nov 17, 2003
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    Do you still think this is the case? Most of the work I do is in R&D and I can say that we (like most others in R&D) prototype using VHDL, but as for further down the production chain I cannot comment.

    One thing that people say to me is that Verilog is easy to use if you are familiar with programming in C (I assume this is because Verilog has some of its history emmanating from the C-Programming language). I really should look into it more.

    Dave
     
  12. n9352527

    AAC Fanatic!

    Oct 14, 2005
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    I should have qualified my statement stronger, that the industries I was referring to and have experience on in this case are mainly ASIC and IC designs.

    At that time, prior to 93 rev. of VHDL, Verilog handled gate and transistor abstraction levels better than VHDL. For example, delay (timing) model and defined primitives. VHDL evolved prior to rev. 93 to counter this through VITAL initiatives.

    Since the beginning, VHDL always was geared and more suitable to higher level of abstraction than Verilog. Mostly at system and behavioural levels. They both sort of overlapped in the mid abstraction levels and Verilog showed its strength at lower hardware related abstraction levels such as RTL, gate and transistor. It was just easier to define a more closely related HDL to hardware structure in Verilog rather than VHDL. It was also a lot faster and required less memory to simulate Verilog hardware related HDL.

    VHDL does have its strengths as a language, structures, strictly typed and library facilities are a few examples of these.

    One thing that I didn't quite understand was most of universities in the UK that I know of at that time offered VLSI/IC design courses with VHDL as their main tools while most of their VLSI/IC industries were using Verilog. If those were digital system design/simulation courses, then VHDL would've been fine. I guess they just lumped digital system design together with VLSI design and treated them as equal. Is digital system design the area in which you are using VHDL Dave?
     
  13. Dave

    Retired Moderator

    Nov 17, 2003
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    Well, when I was at University, I studied Electronic Systems Engineering which meant that we focused heavily on seperating out the individual strains of electronics - DSD being one of them along side VLSI Circuit Design and Implementation etc. We did a rudimentary course in DSD which focused around the seperate design tools and view points, HDLs, rudiments of DSD components (combinatorial, sequential, and FSM [both control and data] design), design methodologies through to implementation issues. So we covered a scatter-gun of subjects, though it was focused around HDLs (particularly VHDL). The VLSI subjects I undertook later focused more around implementation and testing stategies and issues, and the low-level design issues of VLSI components. As it happened I didn't move into that area, but still enjoy analysing and understanding digital circuits and their implementation.

    Nowdays, things have changed. I work mostly on R&D with imaging (mostly Tomographic) techniques. When we look at implementing hardware to use for Data Acquisition and Signal Processing of the image data, if we cannot utilise dedicated hardware, we use fast-prototyping with FPGAs, most of the (hardware) programming development work is done using VHDL. We could quite as easily use Verilog, but the engineers I work with are content with using VHDL (and this is suitable for standardising the process). After we have done the prototyping we often send process specifications to the design engineers who will either look at implementing the designs we have already done on the FPGAs, or go more towards a custom design (largely depending on cost and time constraints and requirements). At this stage in the process we only advise, although to be fair we have a large amount of sway and what we recommend is largely adhered to.

    The main point to be taken from what I have said above is that we utilise VHDL programming on FGPAs for fast prototyping and because of its standardisation across our work. The nature of development work means that we are not concerned with code or implementation optimisation, as long as we can optimise the SP-process we are generally happy. Code optimisation and commercial implementation is generally the concern of the design engineers. I am interested in hearing what happens further down the development line, but this often goes beyond the work I am expected to do.

    n9352527, are you involved in the DSD process? If so, do you find that Verilog is superior to VHDL or vice versa and in what context are you using either HDL?

    Dave
     
  14. n9352527

    AAC Fanatic!

    Oct 14, 2005
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    I'm mainly involved in hardware implementation of digital IC designs. We work on verified behavioural HDL models of the design and decomposed and synthesised them into suitable HDL models according to the target implementation hardware or processes. We also do verifications on some or parts of the design in FPGA.

    The resulting structural/implementation models are then mapped to standard cells or cores that we have or supplied with and then further simulated for initial timing closure and power analysis. After initial layout process the layout dependent parameters such as timing and power are extracted and back-annotated to the HDL and then the design is further optimised and refined to meet the specifications. These are highly iterative processes and very time consuming.

    The main reason of using Verilog over VHDL is that the process of back-annotating the delay from the extracted layout to the HDL codes are supported by Verilog through the SDF (standard Delay Format) earlier than similar VHDL support through VITAL (VHDL Initiative Towards ASIC Libraries). As the consequence, many vendors that we deal with supply and support only Verilog models and libraries instead of VHDL. It was just not possible at that time to reliably include and back-annotate the timing information with VHDL. It is currently more of chicken and egg situation. We don't want to move to VHDL because the supports are not there, and it is rare to find good supports because the market is limited.

    Other advantages of Verilog in this case is its close relationship with hardware structure and faster/requires less resources than VHDL in simulation (we spend so much time and money here so that a little bit of speed difference translate to a quite substantial sum).

    I also do development work with VHDL. These are not geared towards IC designs and mostly are projects targetted at FPGA implementations for development support hardware. I use VHDL because the customers mostly work with VHDL and accordingly expect their supports and supplied codes in VHDL.

    In my opinion, there is no general clear cut conclusion that VHDL or Verilog is the best tool. More like choosing the right tool for the job.
     
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