What is the terminology used to describe segmenting a data bus into smaller pieces, to enlarge the address space and/or shorten bus segment lengths?

Let's say you have a bus that only supports 32 devices, but you want to talk to 256 devices.

So you make a bus of buses:

Bus 0, Address 0 - 30 ( 31 devices + interconnect, 0 - 30)
Bus 1, Address 0 - 30 ( 31 devices + interconnect, 31 - 61)
Bus 2, Address 0 - 30 ( 31 devices + interconnect, 62 - 92)
Bus 3, Address 0 - 30 ( 31 devices + interconnect, 93 - 123)
Bus 4, Address 0 - 30 ( 31 devices + interconnect, 124 - 154)
Bus 5, Address 0 - 30 ( 31 devices + interconnect, 155 - 185)
Bus 6, Address 0 - 30 ( 31 devices + interconnect, 186 - 216)
Bus 7, Address 0 - 30 ( 31 devices + interconnect, 217 - 247)
Bus 8, Address 0 - 7 ( 8 devices + interconnect, 248 - 255)

If I wanted to do this with say I2C or RS-485 what is the chip called that handles communication between the segments?

Is this a bridge, interconnect, span, gateway, daisy-chain, segment...?

Can this be bidirectional between devices on each segment, or is communication primarily initiated by a master controller on the outer bus?

 

What is this in reference to? USB, PICs, CPUs, what?

 

This would be for a huge array of PICs. I'll post about that separately.

This is planning for a capability for expansion, say as a random large value, 2048 PICs.

I see that I2C maxes at 1024 devices, RS-485 at 32.

(Yes, I am aware the cost of 2048 PICs would be... rather high.)

 

What is the terminology used to describe segmenting a data bus into smaller pieces, to enlarge the address space and/or shorten bus segment lengths?
...

If I wanted to do this with say I2C or RS-485 what is the chip called that handles communication between the segments?

Is this a bridge, interconnect, span, gateway, daisy-chain, segment...?
...

I'm not exactly sure what you are doing but it sounds like some type of "node" driver;

main uc -> 10 node driver ucs -> 100 output ucs

You may even be able to get dedicated node drivers, i think they use them in massive LED arrays and the like.

 

Some PICs have two (2) I2C ports.

So maybe use these as "node" controllers, and then you also get "node node" controllers, using USB link, and one big master controller.

If I would have to develope something like this for money, I would not do it at home, but hire experienced engineer/programmer. Because it is not my specialization.

The method of layout mainly depends on the data rate you need. If you have high volume data, you would not use I2C except maybe on the downend.

I2C has 400 KHz max, and you can divide this by 16 or 20 at least to get total kBytes/sec. Even if it might be possible to work it at more than 400 KHz in some cases.

 

I recognize this is likely an obscure situation, especially with I2C's 1024 device limit.

But if there is already a standardized inter-segment controller available to do this, then there would be a library of commands for talking to other segments, and it doesn't all have to be designed from scratch.


(Should this thread be somewhere else?)