Hi all, so I found this SPICE model for a Lithium Ion battery and I tried to import it into Multisim using the component wizard but it gives me several errors. Even if you don't know Multisim I think you can help me since I think the error is within the SPICE model itself. BUT, it might be my node mismanagement in Multisim that's causing me errors.
Errors:
------ Checking SPICE netlist for Design1 - Thursday, February 17, 2011, 1:22:38 AM ------
SPICE Netlist Error in schematic RefDes 'u1', element 'table': Not enough nodes found
SPICE Netlist Error in schematic RefDes 'u1', element 'table': Not enough terminals for device type 'Tranline'
SPICE Netlist Error in schematic RefDes 'u1', element 'liion3__lithium_ion_battery__1': Due to errors, the component 'table' has been omitted from the simulation
SPICE Netlist Error in schematic RefDes 'u1', element 'xu1': Not enough nodes found
======= SPICE Netlist check completed, 4 error(s), 0 warning(s) =======
Code:
* LIION.CIR
* POLYSTOR ICR - 18650
* Lithium-Ion Battery MACROMODEL
* By: Sean Gold
* Originated. 1 11611 996
* Version: 1
* Last Updated: 11/18/1996
.SUBCKT LIION
* Subcircuit Nodes *
+ PLUS MINUS SOC RATE CELL_TEMP
; PLUS + Cell connection
; MINUS - Cell connection
; SOC State Of Charge output node
; 1V=100%, 0V=0%
; RATE Instantaneous discharge rate
; 1V=C, 4 v 4 c
; CELL_TEMP Cell temperature output node
* Subcircuit Parameters *
+PARAMS: CAPACITY=1.25, RESISTANCE=0.08
+TAMBIENT=20, THETA=19.6, HEATCAP=31.5, CYCLE=0
; CAPACITY Cell capacity in AmpHours,
;1=1A-Hr, 0.5e0.5A-Hr
;measured at 1 hour rate
;Cell resistance in ohms
;Ambient temperature in degrees
;Thermal Resistance of the Cell (CnV)
;Heat Capacity ofthe Cell (W*s/C)
;0=NEW 1000=USED
; RESISTANCE
; TAMBIENT
; THETA
; HEATCAP
; CYCLE Number of CYCLES
* DISCHARGE RATE CALCULATION *
E_RATE RATE 0
+VALUE = { I(V_SENSE)/CAPACITY }
* T=R_RATE*C_RATE=3s provides 9s to 15s delay.
R_RATE RATE 40 1
C_RATE 40 0 3
* DISCHARGE AND STATE OF CHARGE *
* Current Controlled Current Source *
G_DISCHARGE SOC 0 VALUE = { I(V_SENSE)}
* LOST CAPACITY DURING FAST DISCHARGE DELAYED
* BY T=R_RATE*C_RATE *
E_LOSTRATE 50 SOC TABLE { V(40) } =
+(0.2 0 )
+(0.5 0.0097 )
+(1 0.0330 )
+(2 0.0650 )
+(3.2 0.0800 )
+(4 0.0900 )
* AMP-HOUR CAPACITY OF BATTERY *
R_CAP 50 0 1G
C_CAP 3D 0 {3600 *CAPACITY * (1-CYCLE*4e-4)}
*
* (1-CYCLE*4e4) Correction for Cell Age
* CAPACITY Parametric Capacity
* 3600 (s/Hr) Time Scale Factor
* CELL TEMPERATURE CHANGES DUE TO POWER DISSIPATION
*THE VOLTAGE AT CELL-TEMP IS ANALOGOUS
*TO CELL TEMPERATURE *
E_RISE 60 0
+VALUE = { (PWR(I(V_SENSE),2) * RESISTANCE * THETA) }
V_AMBIENT 70 60 {TAMBIENT}
* THERMAL TIME CONSTANT *
R_THERMAL CELL_TEMP 70 { THETA*HEATCAP}
C_THERMAL CELL_TEMP 0 1
* CELL RESISTANCE *
R_CELL 20 30 {RESISTANCE}
* CELL VOLTAGE TEMPERATURE COEFFICIENT *
E_TEMP 10 20 TABLE { V(CELL_TEMP) } =
*
+(-20 -0.65 )
+(0 -0.25 )
+(20 0 )
+(40 0.03 )
+(60 0 )
* CURRENT SENSE *
V_SENSE MINUS 30 0
* COMPENSATE FOR INVERTED DATA IN CELL VOLTAGE
TABLE
* OUTPUT VOLTAGE VS STATE OF CHARGE * *
E_COMP COMP 0
+TABLE { V(SOC) } = (-0.1,1.1)(1,0)
R_COMP COMP 0 1G
* Discharge table for PolyStor ICR - 18650
* Lithium-Ion Battery, at C/5 discharge rate.
* Table Consists of:
* Capacity Normalized to 1 V
* I Cell Voltage
*V V
E_CELL PLUS 10 TABLE { V(COMP) } =
+(1.5776E-06 4.1743 ) (6.21496E-05 4.1594 )
+(0.002179096 4.1444 ) (0.007063632 4.1295 )
+(0.0152352 4.1145 ) (0.02538712 4.0996 )
+(0.0367564 4.0846 ) (0.04909088 4.0697 )
+(0.061872 4.0547 ) (0.07563936 4.0398 )
+(0.0901792 4.0248 ) (0.1055504 4.0099 )
+(0.1216544 3.9949 ) (0.1380432 3.98 )
+(0.154712 3.965 ) (0.1713808 3.9507 )
+(0.1880496 3.9364 ) (0.2047064 3.9214 )
+(0.2213752 3.9084 ) (0.2380448 3.8953 )
+(0.2547136 3.8841 ) (0.2713824 3.8741 )
+(0.2880512 3.8641 ) (0.30472 3.8548 )
+(0.3213888 3.8461 ) (0.3380576 3.8367 )
+(0.3547264 3.828 ) (0.3713952 3.8193 )
+(0.388064 3.8106 ) (0.4047336 3.8018 )
+(0.4214024 3.7931 ) (0.4380712 3.7841 )
+(0.45474 3.7744 ) (0.4714088 3.7648 )
+(0.4880776 3.7564 ) (0.5047464 3.7473 )
+(0.5214152 3.7402 ) (0.538084 3.7339 )
+(0.5547528 3.7274 ) (0.5714216 3.7212 )
+(0.5880912 3.7153 ) (0.60476 3.709 )
+(0.6214288 3.7028 ) (0.6380976 3.6959 )
+(0.6547664 3.6885 ) (0.6714352 3.6797 )
+(0.688104 3.6688 ) (0.7047728 3.6555 )
+(0.7214416 3.6411 ) (0.7381112 3.6271 )
+(0.75478 3.6153 ) (0.7714488 3.6019 )
+(0.7841744 3.5869 ) (0.7941312 3.572 )
+(0.802704 3.557 ) (0.81044 3.5421 )
+(0.817808 3.5271 ) (0.82472 3.5122 )
+(0.831672 3.4972 ) (0.838192 3.4823 )
+(0.844496 3.4673 ) (0.850512 3.4524 )
+(0.856416 3.4374 ) (0.86192 3.4225 )
+(0.867448 3.4075 ) (0.872688 3.3926 )
+(0.87788 3.3776 ) (0.882832 3.3627 )
+(0.88764 3.3477 ) (0.892304 3.3328 )
+(0.896928 3.3178 ) (0.901336 3.3029 )
+(0.905528 3.2879 ) (0.909624 3.273 )
+(0.913608 3.258 ) (0.917568 3.2431 )
+(0.921504 3.2281 ) (0.925304 3.2132 )
+(0.929048 3.1982 ) (0.932632 3.1833 )
+(0.936208 3.1683 ) (0.93968 3.1534 )
+(0.94308 3.1384 ) (0.946296 3.1235 )
+(0.949296 3.1085 ) (0.952384 3.0936 )
+(0.95536 3.0786 ) (0.958256 3.0637 )
+(0.961104 3.0487 ) (0.963848 3.0338 )
+(0.966496 3.0188 ) (0.969088 3.0039 )
+(0.971648 2.9889 ) (0.974088 2.974 )
+(0.976504 2.959 ) (0.978736 2.9441 )
+(0.98096 2.9291 ) (0.983128 2.9142 )
+(0.985304 2.8992 ) (0.9874 2.8843 )
+(0.98932 2.8693 ) (0.99112 2.8544 )
+(0.992712 2.8394 ) (0.9944 2.8245 )
+(0.995928 2.8095 ) (0.997352 2.7946 )
+(0.99864 2.7796 ) (0.999888 2.7647 )
+(1.00104 2.7497 ) (1.002064 2.7348 )
+(1.003032 2.7198 ) (1.00392 2.7049 )
+(1.00472 2.6899 ) (1.005472 2.675 )
+(1.006168 2.66 ) (1.006816 2.6451 )
+(1.007416 2.6301 ) (1.008008 2.6152 )
+(1.00852 2.6002 ) (1.00904 2.5853 )
+(1.009552 2.5703 ) (1.010032 2.5554 )
+(1.010528 2.5404 ) (1.011 2.5255 )
+(1.011448 2.5105 ) (1.011744 2.5 )
.ENDS
Thanks,
Kevin
Errors:
------ Checking SPICE netlist for Design1 - Thursday, February 17, 2011, 1:22:38 AM ------
SPICE Netlist Error in schematic RefDes 'u1', element 'table': Not enough nodes found
SPICE Netlist Error in schematic RefDes 'u1', element 'table': Not enough terminals for device type 'Tranline'
SPICE Netlist Error in schematic RefDes 'u1', element 'liion3__lithium_ion_battery__1': Due to errors, the component 'table' has been omitted from the simulation
SPICE Netlist Error in schematic RefDes 'u1', element 'xu1': Not enough nodes found
======= SPICE Netlist check completed, 4 error(s), 0 warning(s) =======
Code:
* LIION.CIR
* POLYSTOR ICR - 18650
* Lithium-Ion Battery MACROMODEL
* By: Sean Gold
* Originated. 1 11611 996
* Version: 1
* Last Updated: 11/18/1996
.SUBCKT LIION
* Subcircuit Nodes *
+ PLUS MINUS SOC RATE CELL_TEMP
; PLUS + Cell connection
; MINUS - Cell connection
; SOC State Of Charge output node
; 1V=100%, 0V=0%
; RATE Instantaneous discharge rate
; 1V=C, 4 v 4 c
; CELL_TEMP Cell temperature output node
* Subcircuit Parameters *
+PARAMS: CAPACITY=1.25, RESISTANCE=0.08
+TAMBIENT=20, THETA=19.6, HEATCAP=31.5, CYCLE=0
; CAPACITY Cell capacity in AmpHours,
;1=1A-Hr, 0.5e0.5A-Hr
;measured at 1 hour rate
;Cell resistance in ohms
;Ambient temperature in degrees
;Thermal Resistance of the Cell (CnV)
;Heat Capacity ofthe Cell (W*s/C)
;0=NEW 1000=USED
; RESISTANCE
; TAMBIENT
; THETA
; HEATCAP
; CYCLE Number of CYCLES
* DISCHARGE RATE CALCULATION *
E_RATE RATE 0
+VALUE = { I(V_SENSE)/CAPACITY }
* T=R_RATE*C_RATE=3s provides 9s to 15s delay.
R_RATE RATE 40 1
C_RATE 40 0 3
* DISCHARGE AND STATE OF CHARGE *
* Current Controlled Current Source *
G_DISCHARGE SOC 0 VALUE = { I(V_SENSE)}
* LOST CAPACITY DURING FAST DISCHARGE DELAYED
* BY T=R_RATE*C_RATE *
E_LOSTRATE 50 SOC TABLE { V(40) } =
+(0.2 0 )
+(0.5 0.0097 )
+(1 0.0330 )
+(2 0.0650 )
+(3.2 0.0800 )
+(4 0.0900 )
* AMP-HOUR CAPACITY OF BATTERY *
R_CAP 50 0 1G
C_CAP 3D 0 {3600 *CAPACITY * (1-CYCLE*4e-4)}
*
* (1-CYCLE*4e4) Correction for Cell Age
* CAPACITY Parametric Capacity
* 3600 (s/Hr) Time Scale Factor
* CELL TEMPERATURE CHANGES DUE TO POWER DISSIPATION
*THE VOLTAGE AT CELL-TEMP IS ANALOGOUS
*TO CELL TEMPERATURE *
E_RISE 60 0
+VALUE = { (PWR(I(V_SENSE),2) * RESISTANCE * THETA) }
V_AMBIENT 70 60 {TAMBIENT}
* THERMAL TIME CONSTANT *
R_THERMAL CELL_TEMP 70 { THETA*HEATCAP}
C_THERMAL CELL_TEMP 0 1
* CELL RESISTANCE *
R_CELL 20 30 {RESISTANCE}
* CELL VOLTAGE TEMPERATURE COEFFICIENT *
E_TEMP 10 20 TABLE { V(CELL_TEMP) } =
*
+(-20 -0.65 )
+(0 -0.25 )
+(20 0 )
+(40 0.03 )
+(60 0 )
* CURRENT SENSE *
V_SENSE MINUS 30 0
* COMPENSATE FOR INVERTED DATA IN CELL VOLTAGE
TABLE
* OUTPUT VOLTAGE VS STATE OF CHARGE * *
E_COMP COMP 0
+TABLE { V(SOC) } = (-0.1,1.1)(1,0)
R_COMP COMP 0 1G
* Discharge table for PolyStor ICR - 18650
* Lithium-Ion Battery, at C/5 discharge rate.
* Table Consists of:
* Capacity Normalized to 1 V
* I Cell Voltage
*V V
E_CELL PLUS 10 TABLE { V(COMP) } =
+(1.5776E-06 4.1743 ) (6.21496E-05 4.1594 )
+(0.002179096 4.1444 ) (0.007063632 4.1295 )
+(0.0152352 4.1145 ) (0.02538712 4.0996 )
+(0.0367564 4.0846 ) (0.04909088 4.0697 )
+(0.061872 4.0547 ) (0.07563936 4.0398 )
+(0.0901792 4.0248 ) (0.1055504 4.0099 )
+(0.1216544 3.9949 ) (0.1380432 3.98 )
+(0.154712 3.965 ) (0.1713808 3.9507 )
+(0.1880496 3.9364 ) (0.2047064 3.9214 )
+(0.2213752 3.9084 ) (0.2380448 3.8953 )
+(0.2547136 3.8841 ) (0.2713824 3.8741 )
+(0.2880512 3.8641 ) (0.30472 3.8548 )
+(0.3213888 3.8461 ) (0.3380576 3.8367 )
+(0.3547264 3.828 ) (0.3713952 3.8193 )
+(0.388064 3.8106 ) (0.4047336 3.8018 )
+(0.4214024 3.7931 ) (0.4380712 3.7841 )
+(0.45474 3.7744 ) (0.4714088 3.7648 )
+(0.4880776 3.7564 ) (0.5047464 3.7473 )
+(0.5214152 3.7402 ) (0.538084 3.7339 )
+(0.5547528 3.7274 ) (0.5714216 3.7212 )
+(0.5880912 3.7153 ) (0.60476 3.709 )
+(0.6214288 3.7028 ) (0.6380976 3.6959 )
+(0.6547664 3.6885 ) (0.6714352 3.6797 )
+(0.688104 3.6688 ) (0.7047728 3.6555 )
+(0.7214416 3.6411 ) (0.7381112 3.6271 )
+(0.75478 3.6153 ) (0.7714488 3.6019 )
+(0.7841744 3.5869 ) (0.7941312 3.572 )
+(0.802704 3.557 ) (0.81044 3.5421 )
+(0.817808 3.5271 ) (0.82472 3.5122 )
+(0.831672 3.4972 ) (0.838192 3.4823 )
+(0.844496 3.4673 ) (0.850512 3.4524 )
+(0.856416 3.4374 ) (0.86192 3.4225 )
+(0.867448 3.4075 ) (0.872688 3.3926 )
+(0.87788 3.3776 ) (0.882832 3.3627 )
+(0.88764 3.3477 ) (0.892304 3.3328 )
+(0.896928 3.3178 ) (0.901336 3.3029 )
+(0.905528 3.2879 ) (0.909624 3.273 )
+(0.913608 3.258 ) (0.917568 3.2431 )
+(0.921504 3.2281 ) (0.925304 3.2132 )
+(0.929048 3.1982 ) (0.932632 3.1833 )
+(0.936208 3.1683 ) (0.93968 3.1534 )
+(0.94308 3.1384 ) (0.946296 3.1235 )
+(0.949296 3.1085 ) (0.952384 3.0936 )
+(0.95536 3.0786 ) (0.958256 3.0637 )
+(0.961104 3.0487 ) (0.963848 3.0338 )
+(0.966496 3.0188 ) (0.969088 3.0039 )
+(0.971648 2.9889 ) (0.974088 2.974 )
+(0.976504 2.959 ) (0.978736 2.9441 )
+(0.98096 2.9291 ) (0.983128 2.9142 )
+(0.985304 2.8992 ) (0.9874 2.8843 )
+(0.98932 2.8693 ) (0.99112 2.8544 )
+(0.992712 2.8394 ) (0.9944 2.8245 )
+(0.995928 2.8095 ) (0.997352 2.7946 )
+(0.99864 2.7796 ) (0.999888 2.7647 )
+(1.00104 2.7497 ) (1.002064 2.7348 )
+(1.003032 2.7198 ) (1.00392 2.7049 )
+(1.00472 2.6899 ) (1.005472 2.675 )
+(1.006168 2.66 ) (1.006816 2.6451 )
+(1.007416 2.6301 ) (1.008008 2.6152 )
+(1.00852 2.6002 ) (1.00904 2.5853 )
+(1.009552 2.5703 ) (1.010032 2.5554 )
+(1.010528 2.5404 ) (1.011 2.5255 )
+(1.011448 2.5105 ) (1.011744 2.5 )
.ENDS
Thanks,
Kevin
