Hi,

This is regarding the SPI interface and XiP (Execute in place) Mode.

1. Do all the SPI serial NOR Flashes support XiP mode?

2. Is there any requirement for a micro processor if it has to be connected to a SPI serial NOR flash with XiP mode support? i.e. let us consider a micro processor which can support SPI flash. If the selected SPI flash supports XiP mode, can the microprocessor communicate with that SPI flash? or the micro processor should have XiP enable feature in its architecture to support such SPI flash?

Please clarify in detail.

 

Hi,

Any reply for this query ?

 

SPI is a serial communication protocol. XiP is a feature of certain types of storage where commands can be run or "eXecuted in Place".

Example: NOR Flash is used to initialize FPGA SRAM configuration at power up, using XiP to Initiate and load configuration over the SPI communication interface.

Your question doesn't make sense. If you have a processor that supports XiP over SPI or with dedicated I/O bus for receiving data from the Flash, it should be well documented. It can be the BIOS on a motherboard that loads microcode to the CPU prior to boot, for example.

Trying to move the results of an instruction over SPI would degrade the speed gains XiP Provides, unless you are talking about XiP on a cached hard drive image (AXFS in Linux).

Both the processor and the storage need to be "aware" of the XiP feature to use it.

As far as Flash Memory type, Look at the addressing in NOR Flash and NAND Flash, do you see any obstacles?

 

Hi,

Thanks for the response.

Both the processor and the storage need to be "aware" of the XiP feature to use it.

If the SPI with XIP feature is connected with the processor which can support Xip, then processor can access the data from SPI in XIP mode or Non-XIP (Standard mode) by setting the register bits. Am I right?


Will the instruction set be different for XiP and Non Xip mode?