# Some Mosfet Questions...

Discussion in 'Homework Help' started by Katie_EE, Apr 11, 2010.

1. ### Katie_EE Thread Starter New Member

Apr 8, 2010
14
0
Any help would be greatly appreciated!

1. Why cant you use a squarewave input voltage to measure a VTC?

I was thinking since all the VTCs for the different Mosfet configurations (Nmos with resistive load, sat. enhancement load,pseudo nmos, and cmos inverter) are all curves...does it possibly have anything to do with the slope? If the input was a squarewave we couldnt read the logic levels since they are calculated using the slope...

and the Slope represents the inverter gain right?

2. I am given a diagram of a Nmos inverter with Saturated enhancement load...with a resistor on top...followed two Nmos transistors in series. The question asks if the resistor were to be replaced by a short circuit, what value of VOH would result and why?

I was thinking perhaps VOH would now equal to VDD ...because there is no resistance...im not sure why...

Thank you!

2. ### Wendy Moderator

Mar 24, 2008
20,772
2,540
When you are asking questions about a specific configuration it is always good to show a schematic. If a picture is worth 1,000 words a schematic is worth 10X that.

3. ### Katie_EE Thread Starter New Member

Apr 8, 2010
14
0
ok i attached the figures i had as a word doc... the second question refers to figure 2.2 B the saturated enhancement load.

I thought about it more would VOH = VDD- VIN if RL is replaced by a short circuit? or would it just equal to VDD?

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4. ### Ghar Active Member

Mar 8, 2010
655
72
The resistor doesn't change VOH.
Look at the very first one, resistive load.
VOH is VDD because the resistor will pull up all the way.

The reason the pull up NMOS doesn't work very well is because it requires at least the threshold voltage across gate-source to conduct. Since gate and drain are connected the source voltage will be the drain voltage minus the threshold. It won't go to VDD.

Of course, you can just simulate it without the resistor using LTSpice or something...

Katie_EE likes this.
5. ### mehta_manish New Member

Apr 4, 2010
3
0
In graphs, V2 and V3 points are not clear w.r.t. schematic. Red curve seems to be at output. In NMOS, pull-up of Gate with Drain will not work as Vgs(th) will not be met i.e. Gate has to be higher than souce by threshold for NMOS to be 'ON'. PMOS has to act as load.