1) Which is the commonly used universal gate and why (between NAND n NOR) ?
2)What is the basic differences between C and VHDL ?
3)How does the device scaling change for NOT,NAND,NOR ?
4)What is set-up time and hold-time in case of flip flops ?
5)Why is BJT more faster than MOS devices ?

 

1) Which is the commonly used universal gate and why (between NAND n NOR) ?
...

Althought it is possible to build any logic circuit using only NAND or only NOR gates, both NAND and NOR are used for reasons of simplicity. Basically you would need 4 NAND gates to mimic a NOR gate and vice versa. So, in order to use less transistors, both NAND and NOR gates are used in logic chips (keep in mind that a NOT gate is a NAND or NOR gate with one input).

I think the first question is answered.

 

VLSI circuits are generally implemented using CMOS technology. The most common gate type is NAND because the pMOS pull-ups are in parallel as opposed to series in NOR gates. Why is this a problem? Because pMOS transistors are slower than nMOS transistors due to the relative mobility of electrons and holes.

Dave

 

1) Which is the commonly used universal gate and why (between NAND n NOR) ?

Answer given above.

2)What is the basic differences between C and VHDL ?

C is a procedural software programming language for writing programmes. VHDL is a hardware description language decrbing hardware structure or behaviour. A quick search on the net should give you more specifics on the differences between these general classes of programming languages.

3)How does the device scaling change for NOT,NAND,NOR ?

Typically the scalling rules are applied on a transistor level. Can you clarify what you mean by this question?

4)What is set-up time and hold-time in case of flip flops ?

The data input to a FF must be stable for some period of time around the clock-edge of the FF if it is to be reliably sampled. The input must settle some time (this is the set-up time) before the edge of the clock, and should not change till some time after the clock-edge (this is the hold time).

5)Why is BJT more faster than MOS devices ?

In VLSI (CMOS) circuits, this is because the output form one logic gate drives the input to another logic gate. In CMOS in the inputs to a logic gate drives the gate of two MOSFETs - this increases the associated RC time constant resulting in the general operation being slower.

Dave

 

What you had were not doubts -- they were questions. This mistake is so common I thought I should remind you. A question is something you ask when you don't know the answer. A doubt is something that you have when you know the answer, but you are uncertain or unsure of your belief.