i composed the following program.


module division_try(/*divisor,dividend,*/quotient,remainder);
output [3:0] quotient;
output [3:0] remainder;
//input [3:0] divisor;
//input [3:0] dividend;

reg [3:0] divisor='b10; //initialise
reg [3:0] dividend='b1010; //initalise


reg [3:0] divisor_alias;
initial
divisor_alias=divisor;

reg [3:0] quotient;
initial
quotient=dividend;


reg aMSB_old;
reg [3:0] remainder;
reg[7:0] concat_aq;
integer n;


always
begin

for(n=0;n<4;n=n+1)
begin
concat_aq={remainder,quotient};
concat_aq=concat_aq<<1;

if(aMSB_old)
begin
adder4 ////ERROR HERE////////////////////////
A1(remainder,divisor_alias,'b0,remainder);
end

else if(aMSB_old==0)
begin
sub4 /////ERROR HERE////////////////////////
A2(remainder,divisor_alias,'b0,remainder);
end

aMSB_old=remainder[3];

case (aMSB_old)
1: quotient[0] = 0;
0: quotient[0] = 1;
endcase
end

if(aMSB_old)
begin
adder4 /////ERROR HERE////////////////////////
A3(remainder,divisor,'b0,remainder);
end

end
endmodule

and when i synthesized the code(the modules for adder4 and sub4 which they themselves call another another submodule each)
I wasnt able to synthesize
i got the following error message

ERROR:HDLCompilers:26 - "division.v" line 57 unexpected token: 'adder4'
ERROR:HDLCompilers:26 - "division.v" line 63 unexpected token: 'sub4'
ERROR:HDLCompilers:26 - "division.v" line 77 unexpected token: 'adder4'

have i gone wrong in the flow??.....are v not supposed to use continuous statements inside a procedural block??....(in my case i have tried using assign-deassign & force-releasse also but in vain....

can u ppl help me??...

 

It would have been helpful to mention you're programming in Verilog.

Here's a Verilog manual:
http://www.stanford.edu/class/ee108b/labs/verilog_reference.pdf

Looks to me like you are attempting to declare functions, but are doing so improperly.
Have a look at the manual, beginning page 5-4 (114th page).