Just a quick question really...I currently have a pic18f sending data to and from a basic stamp 2 chip over a 4 bit bus with an added enable line. I was wondering, would it be ok if 2 bs-2 chips shared the same 4 data lines but either was only activated when it's individual enable signal was high...

I'm just wondering if there would be any issues of sinking the current between processors when only one is being communicated with

Cheers

 

I was wondering, would it be ok if 2 bs-2 chips shared the same 4 data lines but either was only activated when it's individual enable signal was high...

Aren't there different models of basic stamps?
Please provide model and/or datasheet/manual.

 

No problem with that scheme as long as only either the PIC or the Stamp is the "talker" at any given time.

Choose who gets to be "master," the chip drives a direction line, and who is the slave that polls for its direction. There should be some planning for delays so both devices never talk at the same time.

 

fantastic, thanks for getting back to me. The chips communicate well, I was just a little concerned that the 5v logic output may be sunk by the output pins of the stamp I am not trying to access...thanks for putting my mind at rest

 

Ummm... as long as only 1 of the three devices is an output on a common line all should be fine.

<chuckling> Well I think I misunderstood your first post but glad it worked.