No. The UP pin must be HIGH if you want to count down. The DOWN pin must be HIGH if you want to count up. Whichever way you are counting, the other pin must be HIGH, as stated on the datasheet.

This will go a lot faster if you post your current circuit schematic including wiring to external switches.

ak

I hope this explains everything clearly. Switches can be anything. either High and Low (debounced), or push button to ground.


side question: since I only have few 104 and 103 Capacitors left. is it ok to use the equivalent Polarized Capacitor?those aren't very clear to me.

 

There are no Schmitt trigger circuits in your schematic. The way you have them wired, a SPDT switch does not perform any kind of signal conditioning function. It is no better than a SPST switch and a pull up resistor.

IF - in your schematic both switches are shown in their rest positions, then this is not the right way to drive the clock inputs. Also, even if this worked the counters will not increment until the switches are returned to their rest state. Is this really the way you want the switches to operate? Usually a counter changes when the switch is first pushed, not when it is released. That way you get the new counter value right away, no matter how long the switch is held.

Again, the counter changes state on the *positive* edge of the inputs. The other input ***must be in the low state*** for the part to function correctly. This is why there are no bubbles on the two clock inputs. To correct your circuit, reverse the Vcc and GND connections to the switches. P, the single pulse, should be L-H-L.

Again, you need to debounce the switches. With each switch action, the counter input goes from connected to floating to connected. This will not assure proper operation because a TTL input stage floats high. Think of the chip as having a 100K resistor from each input to Vcc. False clock transitions caused by switch bounce will happen, especially when the switch is making contact with GND. Toggling the clock inputs from Vcc to GND may feel like a method to reduce or eliminate the effects of contact bounce, but in fact it does not. Since you already have SPDT switches, to condition two clock signals the best way requires one quad NOR gate IC and four pulldown resistors. The NOR gates form two flipflops, one for each switch.

ak

 

Hi

This might help.

Attached is a graph showing the circuit counting up and a graph showing the circuit counting down.
Each press of the PB generates a short pulse to trigger a count.
I didn't show anything for resetting the counter.

 

I'm not an expert... so I am glad if you can teach me something... but why use a debouncer at the trigger of a 555? It's important if the monostable time is very small, but the OP said 100ms, that I think it's ok for debounce!

Yes. It probably is...but it doesn't mean that a crappy switch won't bounce longer than 100ms.

But there is a different problem with your circuit. The 555 output will go low and stay low as long as the button is pressed. The trigger input must recover in less time than the 555 timeout duration (~110ms). I don't know about you but I can't press and release a button within 100ms.

So I used a single pulse input, of about 20ms, as the trigger signal. When the button's pressed, it causes C5 to discharge through R6, creating a negative going spike on the trigger input, and starts the timer. Holding the button down has no effect since C5 can't recharge until the button is released.

 

But there is a different problem with your circuit. The 555 output...

That's what I was talking about in post #10. What is needed here is a true monostable circuit, one that has positive feedback to ensure that the output pulse width is independent of the trigger pulse width. A 555 monostable configuration has two comparators and a flipflop, but no internal or external feedback.

The pulse shaping circuit in post #23 has promise, but I think the time constants are too short with the components shown. I'll see if I can get a schematic out tomorrow.

ak

 

Thanks Guys, I appreciate the help.
I think that's all the info you needbto help me.
Just a any switch input. And a single pulse output that doesn't wait for the input to reset. And I'll do the rest.
Sorry if I still didn't have the time to feedback for the new solution you gave. There's alot of stuff going on and I need to pick up some ceramic Caps in the city. Life's hard.

I will upload a schematics for the whole project when I finished making the version 2 with the missing single pulse that I needed. And I am reading your replies everyday.

 

But there is a different problem with your circuit. The 555 output will go low and stay low as long as the button is pressed.

What are you talking about?
Look at my circuit, there is an RC at the trigger input, if the RC constant is less than 100 ms the trigger has a positive voltage after the pulse of 100ms and output stay high.

 

What are you talking about?
Look at my circuit, there is an RC at the trigger input, if the RC constant is less than 100 ms the trigger has a positive voltage after the pulse of 100ms and output stay high.

But that's not what the OP showed in the graph in post #1...The duration of the button press varies but the output is normally high and goes low only for 100ms.

 

I don't understand...
Try my circuit please. It does exactly what the OP draw in post n.1. You can press for 1 ms or for 1 minute, you will have at the output of the 555 an high for 100 ms, that you can invert with the transistor. I don't see the problem.

 

@paofanello
How do you propose to discharge the cap on pin 2 of the 555, so that the 555 can be re-triggered if required?

 

But that's not what the OP showed in the graph in post #1...The duration of the button press varies but the output is normally high and goes low only for 100ms.

I don't understand...
Try my circuit please. It does exactly what the OP draw in post n.1. You can press for 1 ms or for 1 minute, you will have at the output of the 555 an high for 100 ms, that you can invert with the transistor. I don't see the problem.

Thanks everyone. eetech00's circuit does what I need. and it's minimal. thanks everyone! thank you paofenallo. I didn't have a chance to try your suggested circuit cuz I don't have some of the components needed.

ak

thanks to you too AnalogKid.

 

This circuit uses a single hex inverter chip to create two monostables with inputs that have extra added hysteresis, and are terminated and current limited for transient protection. Also, the output pulses are the correct polarity.

ak

 

This circuit uses a single hex inverter chip to create two monostables with inputs that have extra added hysteresis, and are terminated and current limited for transient protection. Also, the output pulses are the correct polarity.

ak
View attachment 91735

Looks good. can I use NAND or NOR gates as alternative for NOT gate in this circuit? and any diode? for testing purpose. my 74LS04 ICs are on delivery.

Hi

This might help.

Attached is a graph showing the circuit counting up and a graph showing the circuit counting down.
Each press of the PB generates a short pulse to trigger a count.
I didn't show anything for resetting the counter.

I can't get this one to trigger a count.

 

"I can't get this one to trigger a count."

Recheck your connecions. Make sure you have a bypass cap (0.1uF or 0.01uF) from each IC's positive supply pin to ground.

 

How do you propose to discharge the cap on pin 2 of the 555, so that the 555 can be re-triggered if required?

You are right! This is the circuit:

 

Looks good. can I use NAND or NOR gates as alternative for NOT gate in this circuit? and any diode? for testing purpose. my 74LS04 ICs are on delivery.

The 74AC14 is a CMOS hex inverter with hysteresis, and in this circuit is equivalent to a CD40106. Normally, substituting a non-hysteretic part might cause problems, but because the circuits have external hysteresis applied it should be ok. Yes to any diode, but signal diodes like the 914 and 4148 are faster than power diodes like the 4004.

However: The resistor and capacitor values are selected for CMOS input stages. If you are limited to LS parts, I can recalc. The changes are significant.

ak

 

can I use NAND or NOR gates as alternative for NOT gate in this circuit?

Tie the inputs of a NAND gate together and you get a NOT gate.

Here is one that may be simpler to build. It acts on the rising edge and the time constant is determined by R1/C1.

The use of a diode to charge or discharge a capacitor is fairly common for this type of applications.

 

Here is one that may be simpler to build. It acts on the rising edge and the time constant is determined by R1/C1.

The output pulse width is not independent of the input pulse width. It is equal to the input pulse width plus the RC delay. An independent output pulse width was requested in post #1.

ak

 

You are right.

The oldest trick there is to use a r/c network to generate a pulse.

Would this one work? If the output phase is off, just add a NAND gate there.

 

It will work under some conditions, but only if the input pulse is long enough for C1 to be discharged through D1 and the U1A output stage. At this point you already have two gates, so a true monostable can be had by rearranging the parts already there. Only positive feedback will ensure a consistent output pulse width.

Also, a downward pointing arrow denotes either a negative power supply rail or GND.

ak