single cycle processor mips 32 bit (data memory)verilog help

Discussion in 'The Projects Forum' started by FUNJOKE, Apr 6, 2010.

  1. FUNJOKE

    Thread Starter Member

    Feb 16, 2009
    11
    0
    am working with the single mips cycle processor data memory part ,and i am facing problem with the verilog of data memory ...here is my code ...


    // Data memory
    // It doesn't have a memory read output
    module DM(dataread,clock,memwrite,addr,datawrite);

    input [31:0] addr,datawrite;
    input clock, memwrite;
    output [31:0] dataread;

    reg [31:0] memcell [0:3]; // 4GBmemory cells


    assign dataread = memcell[addr[6:0]];

    always @(posedge clock)
    begin
    if (memwrite == 1) memcell[addr[6:0]]=datawrite;
    end

    endmodule
     
Loading...