a sine wave was applied to a transmission gate as an input voltage when the gate was ON and when it was OFF. then the output was generated on the scope. please! how do you explain the scope output when the gate was ON and when it was OFF .

 

It would help to have the test setup and know what the "transmission gate" (analog switch?) was. Perusing the data sheet for the gate might shed light.

 

Hello,

As beenthere told you, a schematic would help us to give a decent explanation.

Bertus

 

thank you very much for the interest. I uploaded a schematic of the circuit:.
the part used to construct the CMOS T-gate is AOP605. the following link is for the datasheet: http://www.aosmd.com/pdfs/datasheet/AOP605.pdf

 

What is the signal source for A and A-Not?

 

the signal source for is +5VDC.

 

the signal source is +5VDC.
when the gate is on: A = +5vdc, A*= 0
when the gate is off: A = 0, A* = +5VDC

 

Take a look at the first illo in the data sheet. Notice the body diode inherent in the FET's. The off conduction is simply half wave rectification through one of those body diodes.

 

the problem is that when I applied +5vdc to V(in), V(out) = 0 when the gate is off, and V(out)=+5vdc when the gate was on.
if the

 

but when I applied a sine wave at V(in), no matter what the gate state, I still get voltage out.

 

I'm confused, which is not too unusual. It seems that to stop any signal from going through, both A and A* should be 0 V. To get full wave throughput, both should be +5 V. What am I missing?

OOPS: Just now saw Beenthere's response about the diodes! Totally missed that since I had only looked at the OP's original sketch instead of going to the datasheet.

 

the gate A is for an nomos that it's channel get inverted with logic high( +5vdc in this case). and A* gate is for a pmos that get activated with 0 logic.
the gate works as intended when we apply +5vdc as V(in), which means when the T-gate is on V(out) = V(in), and when the gate is off V(out)= 0V.
I get that, the irony is that I cannot explain what happen when the sine wave is applied as V(in).
please refer to previous posts to see how the gate works

 

Thanks for straightening me out. I need to look more closely at the arrows!

 

This might be farfetched, but try this: Connect the substrate (middle arrow) of the PMOS to the Vcc and the substrate of the NMOS to the Ground. Tell us if you see anything different.

I would also like to ask if this is an actual lab experiment, because the transmission gate is a digital circuit, meant to work with logic levels, not analog signals.

 

The devices used don't seem to have the substrate / body diodes accessible other than by the source terminals. If this is so, then it will not be so easy to back-bias the body diodes. Note with the complementary FETs connected in opposite senses, the body diodes are in the same direction, so as to turn on for the negative half-cycle.

In addition, the gates are driven between 0V and +5V only, not to any negative voltage. Because of this, negative signal excursions may tend to turn the NMOS channel on.

 

Not all transmission gate applications are digital, although for analogue applications it may be preferable to refer to such devices as analogue switches. Some manufacturers offer transmission-gate based products intended for analogue switching. Here is a rather old one, analogue or digital: http://www.national.com/ds/CD/CD4066BC.pdf

 

thank you all for your comments