I'm having a bit of a hard time understanding the mechanics of setting criteria up in which to have my block diagram/VHDL projects in Quartus II. I know how to get there and alter it all, so I'm not asking how to do it.

I'll just use an example from one of my labs:

The block diagram is called majority_vote. In VHDL the architecture is:

y< = (d2 and d1) or (d1 and d0) or (d2 and d0)

The truth table is as follows:

A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

In the example, it explains the simulation criteria for the inputs as:

Start value: 000
Increment by: 1
Count every: 10.24 us

I entered it in as such because it told me to, but I don't understand exactly what dictates how I set up my simulation criteria for simulating my block diagrams via vector waveform.

I've looked on the internet for information, but haven't really found anything. If there's something out there to explain this, or if someone would be willing to explain it, I would appreciate it.

 

I can't help you with your simulation software, I have never used it. What I can tell you is that the truth table is wrong.
It should be Σ(3,5,6,7).

 

I am not certain what it is you are trying to do, and this may be too elementary for your purposes. I am in a lab now that employs Quartus and we used the attached Altera document to learn how to implement vector waveform simulation (among other things). Simulation stuff starts on page 23.