Hi,

I wrote a code that only thing that is supposed to do is to chose if the IO bus is input or output.
The module has one input vector(data_in), one output vector (data_out), a clk, an output enable(oena) and the IO BUS (data_inout)


above is the code i used:
(source: http://www.altera.com/support/examples/vhdl/v_bidir.html)

entity inoutleon is
    port(
      
    oena, clk : in std_logic;
    data_out : out std_logic_vector (31 downto 0);
    data_in : in std_logic_vector (31 downto 0);
    data_inout : inout std_logic_vector (31 downto 0));
end inoutleon;

architecture Behavioral of inoutleon is


SIGNAL  a  : STD_LOGIC_VECTOR (31 DOWNTO 0);  -- DFF that stores 
                                             -- value from input.
SIGNAL  b  : STD_LOGIC_VECTOR (31 DOWNTO 0);  -- DFF that stores 
                                             -- feedback value.

BEGIN                                        
    
    PROCESS(clk)
    BEGIN
    IF clk = '1' AND clk'EVENT THEN  -- Creates the flipflops
        a <= data_in;                    
        data_out <= b;                  
        END IF;
    END PROCESS;    
    PROCESS (oena, data_inout)          -- Behavioral representation 
        BEGIN                    -- of tri-states.
        IF( oena = '0') THEN
            data_inout <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
            b <= data_inout;
        ELSE
            data_inout <= a; 
            b <= data_inout;
        END IF;
    END PROCESS;


end Behavioral;

I think everything should work fine, but modelsim refuses to simulate this right.

When the IObus is used as output (oena = '0') is doesn't switches to input.

I've also used a much simpler code but it also doesn't work.

architecture Behavioral of inoutleon is
begin

data_inoutleon <= data_outleon when oena = '0' else (others => 'Z');
data_inleon <= data_inoutleon when oena = '1' else (others => 'Z');


end Behavioral;

Is there a reason for ModelSim to refuse simulating this as expected?
Is there any kind of workaround for this?

Thanks,

 

To me it seems like the VHDL circuit is working just fine. OENA is the enable signal for DATA_INOUT. It acts like a tri-state buffer. When OENA='1', DATA_INOUT is supposed to be your DATA_IN, when OENA='0', your DATA_INOUT goes to "high Z" so it won't short out, or mix signals with anything else. What are you wanting the circuit to do?

 

It's supposed to control the inout port, depending on the oen value.
The thing is that when simulating with modelsim it doesn't work as i think it should.
i've already tryed other ways of doing it, but i can't get modelsim to do it right.

have you tryed to simulate the code i posted in modelsim?