Simulate IO BUS in ModelSim

Discussion in 'Embedded Systems and Microcontrollers' started by ddream, Apr 6, 2009.

  1. ddream

    Thread Starter New Member

    Apr 6, 2009
    2
    0
    Hi,

    I wrote a code that only thing that is supposed to do is to chose if the IO bus is input or output.
    The module has one input vector(data_in), one output vector (data_out), a clk, an output enable(oena) and the IO BUS (data_inout)


    above is the code i used:
    (source: http://www.altera.com/support/examples/vhdl/v_bidir.html)


    Code ( (Unknown Language)):
    1.  
    2. entity inoutleon is
    3.     port(
    4.      
    5.     oena, clk : in std_logic;
    6.     data_out : out std_logic_vector (31 downto 0);
    7.     data_in : in std_logic_vector (31 downto 0);
    8.     data_inout : inout std_logic_vector (31 downto 0));
    9. end inoutleon;
    10.  
    11. architecture Behavioral of inoutleon is
    12.  
    13.  
    14. SIGNAL  a  : STD_LOGIC_VECTOR (31 DOWNTO 0);  -- DFF that stores
    15.                                              -- value from input.
    16. SIGNAL  b  : STD_LOGIC_VECTOR (31 DOWNTO 0);  -- DFF that stores
    17.                                              -- feedback value.
    18.  
    19. BEGIN                                        
    20.    
    21.     PROCESS(clk)
    22.     BEGIN
    23.     IF clk = '1' AND clk'EVENT THEN  -- Creates the flipflops
    24.         a <= data_in;                    
    25.         data_out <= b;                  
    26.         END IF;
    27.     END PROCESS;    
    28.     PROCESS (oena, data_inout)          -- Behavioral representation
    29.         BEGIN                    -- of tri-states.
    30.         IF( oena = '0') THEN
    31.             data_inout <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
    32.             b <= data_inout;
    33.         ELSE
    34.             data_inout <= a;
    35.             b <= data_inout;
    36.         END IF;
    37.     END PROCESS;
    38.  
    39.  
    40. end Behavioral;
    41.  
    I think everything should work fine, but modelsim refuses to simulate this right.

    When the IObus is used as output (oena = '0') is doesn't switches to input.

    I've also used a much simpler code but it also doesn't work.

    Code ( (Unknown Language)):
    1.  
    2. architecture Behavioral of inoutleon is
    3. begin
    4.  
    5. data_inoutleon <= data_outleon when oena = '0' else (others => 'Z');
    6. data_inleon <= data_inoutleon when oena = '1' else (others => 'Z');
    7.  
    8.  
    9. end Behavioral;
    10.  
    Is there a reason for ModelSim to refuse simulating this as expected?
    Is there any kind of workaround for this?

    Thanks,
     
  2. scythe

    Active Member

    Mar 23, 2009
    49
    5
    To me it seems like the VHDL circuit is working just fine. OENA is the enable signal for DATA_INOUT. It acts like a tri-state buffer. When OENA='1', DATA_INOUT is supposed to be your DATA_IN, when OENA='0', your DATA_INOUT goes to "high Z" so it won't short out, or mix signals with anything else. What are you wanting the circuit to do?
     
  3. ddream

    Thread Starter New Member

    Apr 6, 2009
    2
    0
    It's supposed to control the inout port, depending on the oen value.
    The thing is that when simulating with modelsim it doesn't work as i think it should.
    i've already tryed other ways of doing it, but i can't get modelsim to do it right.

    have you tryed to simulate the code i posted in modelsim?
     
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