Simulate a Decade Counter in PSpice?

Discussion in 'The Projects Forum' started by sailmike, Apr 11, 2014.

  1. sailmike

    Thread Starter Member

    Nov 11, 2013
    143
    3
    I need to simulate the output of a decade counter in PSpice. I'm making a LED chaser and need to simulate the counter. The following attachment shows just three MOSFET's for now. I just need to turn on each MOSFET one at a time. Does anyone know how to do that in PSpice?

    Thanks,
    Mike
     
  2. crutschow

    Expert

    Mar 14, 2008
    13,016
    3,235
    It doesn't matter if it's real life or Pspice, you still need a circuit. So why not use a decade counter IC?
     
  3. sailmike

    Thread Starter Member

    Nov 11, 2013
    143
    3
    It's easy to find a 4017 decade counter in PSpice, but it doesn't have a Spice model and I couldn't find one online. That's why I'm asking here.

    Thanks,
    Mike
     
  4. sailmike

    Thread Starter Member

    Nov 11, 2013
    143
    3
    After a lot of searching I finally found a model for a CD4017 decade counter. When I run the simulation I get the error message shown in the attachment. I think the model code is missing some lines, ".model..." something. I don't know what the rest of it is supposed to say. Here's the model code:

    *---------
    * CD4017B CMOS COUNTER/DIVIDER
    *
    * CMOS INTEGRATED CIRCUITS DATABOOK, 1983, RCA SOLID STATE DIVISION
    * NH 9/8/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES
    *
    .SUBCKT CD4017B CLK_I CLKINHIBIT_I RESET_I O0_O O1_O O2_O O3_O O4_O O5_O O6_O
    + O7_O O8_O O9_O CARRYOUT_O
    + OPTIONAL: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
    + PARAMS: MNTYMXDLY=0 IO_LEVEL=0
    *
    U17BBUF BUF VDD VSS
    + CLK_I CLK
    + D0_GATE IO_4000B_ST IO_LEVEL={IO_LEVEL}
    *
    U17BLOG LOGICEXP(13,16) VDD VSS
    + CLK CLKINHIBIT_I RESET_I Q1 Q2 Q3 Q4 Q5 Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
    + CLKINHIBIT RESET CLOCK O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT TOQ3 RST
    + D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
    +
    + LOGIC:
    +
    * BUFFERS
    + CLKINHIBIT = { CLKINHIBIT_I }
    + RESET = { RESET_I }
    +
    * OUTPUT ASSIGNMENTS
    + CLOCK = { ~(~CLK | CLKINHIBIT) }
    + O0 = { Q5BAR & Q1BAR }
    + O1 = { Q1 & Q2BAR }
    + O2 = { Q2 & Q3BAR }
    + O3 = { Q3 & Q4BAR }
    + O4 = { Q4 & Q5BAR }
    + O5 = { Q5 & Q1 }
    + O6 = { Q1BAR & Q2 }
    + O7 = { Q2BAR & Q3 }
    + O8 = { Q3BAR & Q4 }
    + O9 = { Q4BAR & Q5 }
    + CARRYOUT = { Q5BAR }
    + TOQ3 = { ((Q1 & Q2) | (Q2 & Q3)) }
    + RST = { ~RESET }
    *
    UFF DFF(5) VDD VSS
    + $D_HI RST CLOCK Q5BAR Q1 TOQ3 Q3 Q4 Q1 Q2 Q3 Q4 Q5
    + Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
    + D0_EFF IO_4000B
    *
    U17BDLY PINDLY (11,0,4) VDD VSS
    + O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT
    + CLOCK RESET CLK CLKINHIBIT
    + O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O CARRYOUT_O
    + IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
    +
    + BOOLEAN:
    + CH_CLOCK = { CHANGED_LH(CLOCK,0) }
    + CH_RESET = { CHANGED_LH(RESET,0) }
    +
    + PINDLY:
    + O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O = {
    + CASE(
    + CH_RESET, DELAY(-1,265NS,530NS),
    + CH_CLOCK, DELAY(-1,325NS,650NS),
    + DELAY(-1,326NS,651NS) ;DEFAULT
    + )
    + }
    + CARRYOUT_O = {
    + CASE(
    + CH_RESET, DELAY(-1,265NS,530NS),
    + CH_CLOCK, DELAY(-1,300NS,600NS),
    + DELAY(-1,301NS,601NS)
    + )
    + }
    +
    + FREQ:
    + NODE = CLK
    + MAXFREQ = 2.5MEG
    +
    + WIDTH:
    + NODE = CLK
    + MIN_HI = 200NS
    + MIN_LO = 200NS
    +
    + WIDTH:
    + NODE = RESET
    + MIN_HI = 260NS
    +
    + SETUP_HOLD:
    + DATA(1) RESET
    + CLOCK LH = CLK
    + RELEASETIME_HL = 400NS
    +
    + SETUP_HOLD:
    + DATA(1) CLKINHIBIT
    + CLOCK LH = CLK
    + SETUPTIME = 230NS
    + WHEN = { RESET!='1 }
    *
    .ENDS

    Does anybody know what the line ".model..." is supposed to say? If this isn't the source of the error, does anybody know what is?

    Thanks,
    Mike
     
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