Hi!
I'm trying to make the two outputs (Q and /Q) of a D-type flip flop step from high to low, alternating with each other, with every rising edge of a squarewave input (ie a simple switch going to ground). I've never used flip flops before and I'm having real trouble getting it to work!

Attached is the circuit diagram I'm trying.... Have I connected it right?? Any advice is much appreciated!

The two outputs (Q and /Q) will work JFET gates on two audio outputs, so with the flick of a non-latching switch you can step between 'A' output and 'B'.

 

Welcome to AAC!

Tie clear HIGH; with LOW, you force the flip flop to be reset, so Q will always be LOW.

And put a resistor between the switch and 5V.

 

Welcome to AAC!

Tie clear HIGH; with LOW, you force the flip flop to be reset, so Q will always be LOW.

And put a resistor between the switch and 5V.

Thanks so much - will test that out!

This is a handy forum!

 

Hi

If the function you want is "toggle" where Q and /Q and switch between high and low states on the rising edge of the clock pulse you will probably find this easier with a T- type FF or a JK FF.

e.g.

74HC/HCT109 - Dual JK flip-flop with set and reset; positive-edge trigger

Introduction to Flip Flops: D and T

 

Thanks

You're welcomed.

Where did you get the symbol for the flip flop? Technically you either use Q# or a bubble for the inverted output, but not both. Two inversions would give you two Q outputs.

 

If the function you want is "toggle" where Q and /Q and switch between high and low states on the rising edge of the clock pulse you will probably find this easier with a T- type FF or a JK FF.

OP had the D FF connected as a T FF. Just had a problem with reset.

 

OP had the D FF connected as a T FF. Just had a problem with reset.

Definitely, the only concern I had with this topology is the delay introduced but if it's a low enough frequency I doubt it'll matter I suppose

 

Hi

If the function you want is "toggle" where Q and /Q and switch between high and low states on the rising edge of the clock pulse you will probably find this easier with a T- type FF or a JK FF.

e.g.

74HC/HCT109 - Dual JK flip-flop with set and reset; positive-edge trigger

Introduction to Flip Flops: D and T

I should've said each falling edge, not rising.... So would the chip I'm using be any good for that?

 

I should've said each falling edge, not rising.... So would the chip I'm using be any good for that?

The one you have is positive edge triggered so I'm unsure if it will operate as you would require. You could try the 74LS112 which is a negative edge D-type or the 74LS/HC/HCT73 is a JK negative edge triggered flip-flop.

 

I should've said each falling edge, not rising.... So would the chip I'm using be any good for that?

Invert the trigger or get a negative edge triggered flip flop.

 

Invert the trigger or get a negative edge triggered flip flop.

So now I've got this (see diagram) with trigger reversed for rising edge, /CLR tied to 5v, and also added 1k between switch and earth.
It sort of works occasionally, but I'm wondering if there's some sort of major switchbounce event going on....
Or is there something wrong with the circuit still?
Thanks!

 

You need a switch debounce capacitor and resistor...on the clk pin.

 

So now I've got this (see diagram) with trigger reversed for rising edge, /CLR tied to 5v, and also added 1k between switch and earth.
It sort of works occasionally, but I'm wondering if there's some sort of major switchbounce event going on....
Or is there something wrong with the circuit still?
Thanks!

Try making your 1k into a 33k to 100k.

then add a 10uF across the switch.

 

Like this? It works only very occasionally...

 

What clock rate are you using?

 

You need a hex inverter on the clock output before the flip-flop but this additional component maybe justify getting a negative edge JK flip-flop. There will be a delay with this D-type topology but if your clock isn't that fast it should be ok.

 

Like this? It works only very occasionally...

Do you have the other end of the capacitor connected to 5V? A 10uF cap is probably polarized. Do you have it connected correctly? How quickly are you expecting to switch the switch?

 

The switch gets pressed fastest... about twice per second. The 10uF is connected to 5v and is the right way round.

 

The switch gets pressed fastest... about twice per second. The 10uF is connected to 5v and is the right way round.

What D FF are you using? What type of switch are you using? What resistance are you using?

 

Sorry I was under the impression your switch was controlling a stable clock pulse. In that case put the inverter after the switch if you absolutely have to use this positive edge FF.