I have a simple question concerning the operation of a synchronous buck DC/DC circuit. In the standard model most commonly used, a mechanical switch is used to connect the input to the output during the ON state, and a diode is used during the OFF state. When the input is disconnected, the diode forward conducts when the SW voltage falls to ~ -700 mV (diode drop). In this case, the SW node fluctuates from VIN (ON) to ~700 mV (OFF).
For the case of a synchronous rectifier, an NMOS device is used instead of the free-wheeling diode. If my understanding is correct, the drain and source of a MOSFET are symmetrical and can be used interchangeably. That is, current can conduct in both directions when the device is ON (assuming VGS is above Vt).
For the high side NMOS, the current from VIN flows from drain to souce. The drain is held at a higher potential than the source (Vsource = rds(on) x Iin)
For the low side NMOS, however, the current flows from source to drain (if we denote the source as the terminal tied to GND). In this scenario, what happens to the voltage at SW node? Is SW node still negative like when using a conventional diode? Or, can we instead, interchange the source and drain terminals and say that the drain is tied to GND. If we do this, then the source will again be at the lower potential (- rds(on) x IL)? Does it make sense to interpret it this way? I guess it's strange for me to look at the FET and say that the drain would be at a lower potential than the source and still be conducting.
Thanks for the help
For the case of a synchronous rectifier, an NMOS device is used instead of the free-wheeling diode. If my understanding is correct, the drain and source of a MOSFET are symmetrical and can be used interchangeably. That is, current can conduct in both directions when the device is ON (assuming VGS is above Vt).
For the high side NMOS, the current from VIN flows from drain to souce. The drain is held at a higher potential than the source (Vsource = rds(on) x Iin)
For the low side NMOS, however, the current flows from source to drain (if we denote the source as the terminal tied to GND). In this scenario, what happens to the voltage at SW node? Is SW node still negative like when using a conventional diode? Or, can we instead, interchange the source and drain terminals and say that the drain is tied to GND. If we do this, then the source will again be at the lower potential (- rds(on) x IL)? Does it make sense to interpret it this way? I guess it's strange for me to look at the FET and say that the drain would be at a lower potential than the source and still be conducting.
Thanks for the help
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