Silly op-amp power supply question

Discussion in 'General Electronics Chat' started by kdillinger, Sep 10, 2009.

  1. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
    141
    3
    I need another brain this late at night because I am at a loss for an explanation.

    I am using the OPA561 which is a power op-amp from Burr-Brown. It is a class AB output stage and it is configured as a non-inverting gain of 5 driving a 4Ω load The power supply is +15/0V while the load is AC coupled via a 330uF and referenced to circuit common. The input voltage is 2Vp.

    I am measuring the power supply current using a current probe but what I am seeing makes no sense. I fully expect current to be pulled from the supply proportional to the load plus some quiescent current during the positive cycle only. This means Q1 or the pMOS is conducting sourcing current to the load. During the negative cycle the nMOS is conducting sinking current from the cap and load and no current is being pulled from the supply (neglecting quiescent current). The current waveform under this circuit configuration should resemble a half-wave rectified waveform. The peak supply current should be equal to the peak load current if quiescent current is neglected.

    interestingly enough it does, but only at low frequency ~1kHz. If I increase the input frequency to 64kHz the supply current waveform looks like a DC 600mA waveform with ~50mA of ripple. Coincidentally, the DC supply reads 650mA but that should be some averaging function of the supply itself. The voltage across the load remains, as expected, a sinusoid with no sign of slew rate limiting.

    I am expecting to see a half-wave looking waveform even at this frequency as long as the amp is not slew rate limiting.

    What am I missing?

    -Ken
     
  2. bertus

    Administrator

    Apr 5, 2008
    15,646
    2,345
    Hello,

    Can you post a schematic?

    Greetings,
    Bertus
     
  3. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
    141
    3
    This is the best I can do under quick notice. I modified TI's spice schematic. I may go forward and simulate as well.

    **updated schematic**
     
  4. bertus

    Administrator

    Apr 5, 2008
    15,646
    2,345
    Hello,

    The position of the bias is wrong.
    Use the bias at the + input of the opamp via a resistor of 10 K.

    Now the bias is amplified 4 times and the output will clip.

    Greetings,
    Bertus

    PS use PNG or GIF as attachments, DOC needs to load a wordprocessor.
     
  5. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
    141
    3
    The bias is applied to then non-inverting node and the gain resistor so the output will be at Vdd/2 or 7.5V in my case. The common mode gain is 1.

    The current limit was not reflected in my drawing so the current limit flag is tied to common to provide 1.2A.
     
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