Silicon Substrate manufacture

Discussion in 'General Electronics Chat' started by DenisM, Apr 23, 2012.

  1. DenisM

    Thread Starter New Member

    Apr 23, 2012
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    Hi,

    When ICs are being made, how do they engineer resistors within the design, given that it's made from silicon ?
    I can understand how you would make transistors/diodes on the silicon but resistance ?

    DenisM
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    A resistor is fabbed as nothing more than a length of conductor having a nominal sheet resistance. No material has zero resistance, and that is particularly true for materials on an IC. Let's say that you have a strip of material that has been fabbed that is WxLxt where W is the width (the electrical contacts are made on these two sides), L is the length, and t is the thickness. The resistance between the contacts will then be

    <br />
R=\sigma \frac{L}{Wt}<br />

    where \sigma is the resistivity of the material used.

    Since the thickness of the resistor is fixed, we can rearrange this as:

    <br />
R=\left(\frac{\sigma}{t} \right)\left(\frac{L}{W}\right)<br />

    The first factor is defined by the process and is known as the "sheet resistance", which is the resistance of a 1x1 sheet of material. The units are "ohms per square". Note that it doesn't matter (in theory) if it is 1um x 1um or 100um x 100um. So when you lay out a resistor, you are primarily interested in laying it out so that you have a desired number of "squares", which is the L/W ratio.

    If you want pretty low resistance, then you use metal (the same metal you use to connect devices on the chip -- in fact, every trace connecting one component to another is a resistor and, for some parts of some designs, that resistance has to be taken into account. If you don't want the resistance but have to live with it, you call it parasitic resistance. If you want it, then you call it a resistor. Either way, the circuit sees the same thing. Similarly, every trace has capacitance to things around it. So if you put a trace of Metal1 (the first metal layer to be laid down) underneath a trace of Metal2, then you will have some capacitance between them. Whether that is a parasitice capacitance or a capacitor from the circuit design depends on whether you want it there or not.

    For resistors and capacitors, you have a number of options. For small valued resistors you use metal. For intermediate values, you frequently use poly (polysilicon, which is what the transistor gates are made of) and sometimes you have particular implant options you can use in order to get better resistivities (by 'better', it means more useful ranges and/or more uniform and precise resistivities). For larger values you use active (the same material used for source/drain implants) and, again, sometimes you have access to special implants to make better resistors. For very large values, you use a well (which is the bulk implant for transistors). The discussion above is assuming a CMOS process, but similar things are the case for BJT and other processes.

    For non-critical resistors, you can be pretty sloppy with the layout. For resistors where you need good matching to other resistors, things get a lot more interesting. For the most part, you don't even try to make resistors that are highly accurate since the uncertainty in the doping and dimensions really limit that. If you need precision resistors on an IC, you frequently have to resort to laser trimming (read: expensive).
     
  3. DenisM

    Thread Starter New Member

    Apr 23, 2012
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    Thanks for that detailed explanation. I had assumed that a silicon rectangle was etched away somehow to leave residual parts of the silicon and thus form various silicon junctions, but i now see it's a lot more complex.
    When you say 'implant' , you mean material added onto the silicon plate ?
    - say -a layer of some metal or as you said polysilicon?

    Thanks again.
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    As you say, the IC fabrication process is very complicated (and getting more complicated all the time). There are many different ways to fab a chip, depending on what kind of devices are needed and what the important characterists are for the design. So I can only describe a very simplified "typical" CMOS process.

    First off, pure silicon is a lousy conductor. So you have to add impurities to it in order to control how well it conducts. What makes semiconductors useful is that you can control the conductivity of appropriately doped silicon by applying an electric field to it. There are two basic types of dopants, p-type and n-type. Without going into too much detail, just think of the difference as being that in one type of material you want to change the field in one direction in order to increase the conductivity while in the other you want to change it in the other direction. Again, keep in mind that this is a very hand-wavy description, but I think it is good enough for our purposes.

    So how do we get these dopants into the wafer at just the right places that we want? There are a number of ways to do this. One is to simply have the impurities mixed with the silicon in molten form so that they are a part of the ingot from which the bare wafers are originally cut. At this stage you have a uniformly doped wafer, generally with a mild p-type doping. Another way is to expose the wafer to a vapor that has the impurities in it. The parts of the wafer that are no protected by a mask will absorb the impurities with the concentation being the greatest at the surface and tapering off as you go deeper. Another way is to use an ion or molecular beam to essentially shoot the dopant atoms into the wafer. Again, regions that are protected by a mask will not get much of an implant but regions that aren't protected will get a doping concentation that will be greatest at a desired depth and will taper off as you get both deeper and shallower. The key thing in the last two methods is that you can control where, on the wafer, these various implants go, by using photolithography in a manner very analogous to how you make printed circuit boards. You apply a layer of liquid photoresist to the wafer, let it set, expose it using a mask image, apply a developer that either dissolves the resist that was exposed or, depending on the type of resist used, the part that wasn't. You then wash off the dissolved resist and expose the entire wafer to the whatever step you are performing and, when done, you apply a chemical that dissolves the rest of the resist so you can wash it off and move on to the next step by applying a new layer of resist and exposing using the next mask.

    Modern CMOS processes have a couple of dozen masking steps involved. At some steps you are implanting a dopant, while at others you are laying down a new layer of material, such as polysilicon (typically used for the gates of FET transistors and also for resistors and capacitors) or metal layers, or silicon dioxide which acts as an insulator between layers. At some steps you also remove material. For instance, after laying down a metal layer (traditionally aluminum), you cover it with an oxide layer. But you will need to make connections to this layer from higher layers. So you put a mask on that has holes in the mask wherever a connection is needed and then you etch the oxide way to expose the underlying metal and then fill the hole with a conductive metal (tungsten has traditionally been used, but other materials are becoming common) and then when you lay down the next layer of metal, it will connect to these "vias".

    That's a really, really, superficial look at how an IC is made, but hopefully it is helpful for your purposes.
     
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  5. atferrari

    AAC Fanatic!

    Jan 6, 2004
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    You know the subject and how to explain it! Concise and to the point. Great!
     
    Last edited: Apr 25, 2012
  6. WBahn

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    Mar 31, 2012
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    I'm glad you guys liked it and found it useful.

    The general rule is that in a discrete design you can get highly accurate components but that relying on matching between components is not a good way to go. It is the opposite for ICs - you can get really good matching, but don't want to rely on highly accurate values. For instance, most capacitor and resistor values have at least a 20% tolerance but, whatever the absolute value is, you can generally expect to get two of them to match within 1% of each other.

    But while that difference between IC design and discrete design is widely known, what is not appreciated, even by most IC designers, are the subtle lengths that you have to go through in order to actually achieve really good matching. I say 'even most IC designers' because most IC designers are digital designers and good matching is not very important to them, but it is the bread and butter for most analog designs. I was a mixed-signal ASIC designer for about 14 years and was amazed at some of the things you need to take into account. For instance, it's not enough to just make a component the same size, you also want to orient them the same way on the chip and have the current flow the same direction through the component. If you really want tight matching, you interdigitate the two components so that even slight variations in processing across the chip will affect the two (or more) components in nearly identical ways. There are also additional steps that the fab house takes on an analog process compared to a digital process in order to achieve better parameter control and matching. For instance, ion implants are done at an angle (for reasons having to do with the mechanics of making the machinery) and so they might implant a quarter of the implant and then turn the wafer ninety degrees and repeat this three times so as to minimize the orientation effects, but good analog designers still assume high anisotropy (directional variation) in their layouts.
     
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  7. DenisM

    Thread Starter New Member

    Apr 23, 2012
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    Thanks again. You are awesome :)

    D.
     
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