In the SCR operation when the gate current is applied what happens to the Junction J2 and J3. I figured out junction J3 will become more forward biased and the depletion region will thin out because of the positive voltage on the p side of J3, but what about J2?
How does J2 breakdown at a lesser voltage??

I understood the 2 transistor analogy (which I consider a 'black box' model) how is the regenerative action happening within the SCR???

Why does the SCR conduct even if the gate signal is switched off????

Thanks a lot for your help...

 

In the SCR operation when the gate current is applied what happens to the Junction J2 and J3. I figured out junction J3 will become more forward biased and the depletion region will thin out because of the positive voltage on the p side of J3, but what about J2?
How does J2 breakdown at a lesser voltage??

I understood the 2 transistor analogy (which I consider a 'black box' model) how is the regenerative action happening within the SCR???

Why does the SCR conduct even if the gate signal is switched off????

Thanks a lot for your help...

Are you assuming we are looking at the same drawing that you are?
You need to post a picture, or whatever it is you are referring to.

 

 

You mentioned J2 and J3. Do you have a drawing showing J2 and J3?
We are not mind readers.

 

 

Latching holds it on.

Once it is turned on it creates an internal gate current path.

Shut off the circuit to shut off that internal gate path.

The opposite polarity of an AC waveform will likewise turn it off.

 

You say you understand the two transistor model of the SCR. So look at the SCR junctions. The top three junctions are the PNP and the bottom three junctions are the NPN. In the SCR the N base of the PNP is the same as the NPN collector and the PNP collector is the same as the NPN base.

When you apply a positive current to the SCR gate the bottom NPN transistor layers turn on. Since the top PN junction is forward biased it also conducts and the SCR turns on. When the SCR gate signal is removed, carriers are still being injected into the gate region from the top PNP so the NPN layers keep conducting, even with no outside gate current. It keep conducting until the SCR current is reduced to zero and no more carriers are being injected into the base region.

 

After you remove the gate signal only the +ve anode w.r.t cathode remains hence electrons are flowing one way and holes are flowing the other way, now if that is the case then current must necessarily flow in common emitter mode of a transistor with collector-emitter voltage applied and base-emitter voltage removed(i.e 0.7 v)!!!

Why is this happening only in SCR?

What is this regenerative action that is taking place only in the SCR??