I want to generate the signals as attached in the image.
The frequency of these signals should be variable.

Can anybody help me with this

 

1. A processor can generate these signals
2. An FSM in an FPGA can also generate these waveforms from a higher frequency clock.

 

A VCO might be able to do it too.

What is the timing of the pulses? Or if it is that variable, how about duty cycles?

 

Looks to me like the 2st waveform is a cam timing signal from a 6-cylinder engine. The "odd man out" pulse is the TDC signal, but it's sent ahead of time where the actual TDC occurs.

Not absolutely sure what the 2nd waveform is, but it's 58 clocks, then 2 missing clocks.

I guess our OP wants to build a test set for an ignition system.

What's not readily apparent is the timing relationship of the 1st waveform to the 2nd waveform.

Anyway, I think using a 4017 Johnson counter as a /6 gating a clock could be a good start on it.

 

A microcontroller with a crystal could be a good tool for this job.

 

Hello Sgtwookie,

you r right. these are cam and crank signals.

any circuit you can provide would be great.