shift register

Discussion in 'General Electronics Chat' started by gorgondrak, Jan 2, 2015.

  1. gorgondrak

    Thread Starter Member

    Nov 17, 2014
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    A CD4031 64-bit shift register has a Q64 delayed output and a delayed clock output. Does anyone know what these are used for?
     
  2. ericgibbs

    Senior Member

    Jan 29, 2010
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  3. gorgondrak

    Thread Starter Member

    Nov 17, 2014
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    http://www.allaboutcircuits.com/vol_4/chpt_12/3.html

    The SN74LS674 has additional inputs mode and cs. I assume since cs is ANDed to the clock it it a clock inhibitor that needs to be high for the clock to reach the data inputs?? Also mode was previously used to select 2 separate data inputs within the same register, but what is its purpose here?
     
  4. panic mode

    Senior Member

    Oct 10, 2011
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    tsk-tsk.... first thing is to - always read the datasheet! ;)

    for example first link I opened after search for part number in original post, lead to TI datasheet with schematic. delayed clock is same signal as clock but after it passes two inverters (which means propagation delay of two gates)
     
  5. gorgondrak

    Thread Starter Member

    Nov 17, 2014
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    Yes. I'm wondering what a phase shifted clock output could be used for in a shift register. Also, is it outputting the edge of the clock or just a delayed full clock cycle.
     
    Last edited: Jan 3, 2015
  6. BillB3857

    Senior Member

    Feb 28, 2009
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    May be that the delayed clock is to allow the data line to be at a settled state before clocking.
     
  7. ericgibbs

    Senior Member

    Jan 29, 2010
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    The clock options are explained on the first page of the 4031 d/s, refer clip
     
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