Shift register using flip flop

Discussion in 'Homework Help' started by vead, Sep 13, 2016.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
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    Hello
    Please look at the attached document. I have just taken four d flip flops and tried to make shift register. Than I tried to transfer data from one register to another register. If all is correct, I am trying to make universal register that could be read or write. I don't understand how to add read / write function in register?
     
  2. AlbertHall

    Well-Known Member

    Jun 4, 2014
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    You already have serial read and write and parallel read built in.
    If you want parallel write you can use the flip-flop set and reset inputs.
     
  3. ci139

    Member

    Jul 11, 2016
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    if theoretical v. you can add an input address from a decoder
    [​IMG]
    for each of your 4 D-Flops as A0=0 serial input (**Gate-S) A0=1 parallel input (**Gate-P)
    for that add 2x CMOS GATES** before T_GT instead of C-cloud
    [​IMG]
     
  4. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
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    I think I am confused on inputs of register. As you seen, I made shift register using d flip flops. Now there was data input, clock Input and data output. Now I can Say I have shift register has three pins. Data input pin, clock Input pin and data output pin. Now I want to another pin that will store data from another register or that will transfer data to another register. How to make register using d flip flops that will read or write data to another register?
     
  5. AlbertHall

    Well-Known Member

    Jun 4, 2014
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    Do you want to transfer the data serially or in parallel?
     
  6. vead

    Thread Starter Active Member

    Nov 24, 2011
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    I want to transfer data serially. As you can see in my attachment. At bottom there are two diagram that show the data move from one register to another. But I want to create function read/ write function for single register. I saw, many ics has read /write pin. Means it can be store data or it can be transfer data. I am just trying to add this function in my shift register diagram
     
  7. AlbertHall

    Well-Known Member

    Jun 4, 2014
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    So feed your clock to one register and input new data on the input pin and read output data on the output pin.
     
  8. vead

    Thread Starter Active Member

    Nov 24, 2011
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    Hello AlbertHall
    Do you mean like this
    _20160913_231429.JPG
     
  9. AlbertHall

    Well-Known Member

    Jun 4, 2014
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    That connection will read out the data on Q2 while rewriting it in to the two registers leaving the data in the registers unchanged.
     
  10. ci139

    Member

    Jul 11, 2016
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    ? if you connect your Reg.2.OUT back to Reg.1.IN you have 1-st 4 clocks filling Reg.1 with Reg.2 and Reg.2 with Reg.1 and the next 4 clocks filling Reg.1 with Reg.1 and Reg.2 with Reg.2
    where the "Reg.#" is the register being filled with time point after 8 clocks registers content container name named data
    and "with Reg.#" is the data that is filled to the "Reg.#"
    other words by connecting 2 4 bit serial I/O registers creates an 8-bit serial I/O register that is capable of tranferring the data from input towards output only

    *** if you want bi-directional function you have to electronically redirect your data cells inputs and outputs SI→[D0]→[D1]→[D2]→[D3]→SO to SI←[D0]←[D1]←[D2]←[D3]←SO
    if you want there by use SI as output then it is automatically done by the same direction setting signal
    if you still want to have the same bit order and swap the R/W function for SI/SO ports then redirect SO→[D0]→[D1]→[D2]→[D3]→SI
    if you still want to have the same bit order but you want to keep the function for SI/SO ports - then it's where we started from ***

    if you want the data being recycled in the 4-bit serial shift register - you have to add a recycle funtion by a signal enabling disabling the internal recycling as you disconnect the SI× [D3]→[D0]→[D1]→[D2]→[D3]→SO
    whitch is the same as adressing the input lined to your [D0] : as no recycle SO→[D0]... and enable recycle [D3]→[D0]...

    if you want to have extra input storage and output storage buffer registers then your chain changes SI→[SI.buf]→[D0]→[D1]→[D2]→[D3]→[SO.buf]→SO so you can add read&store (in input buffer) the input signal SI and write&store(in output buffer) the output signal for SO -- such makes sense if your shift register is connected to single wire system data bus where is other traffic occuring . . .

    so, futher on if SI and SO is to be read/write to the same data bus you add a single read-write port to your shift register thus extending your chain to : BUS↔[R/W.port]→[electronic switch enabling register loading]→[D0]→[D1]→[D2]→[D3]→[electronic switch enabling register unloading]→[R/W.port]↔BUS

    if you want more flexibility you use :
    BUS-es↔[[[multiple R/W.ports]]]]↔[[[electronic swith enabling register loading]]]]↔[D0]↔[D1]↔[D2]↔[D3]↔[SO.buf]↔[[[electronic switches enabling register unloading]]]↔[[[to multiple R/W.port connected]]]↔BUS-es
    where setting up the internal bi-directionality requires bit-wise I/O redirection (basically forward wiring and backward wiring)
    also and again - where setting up the internal recycle function recuires SI/SO-wise redirection

    you can also add electronically controlled parallel data links e.g. [parallel input port] that has four inputs from parallel input multiplexer and four outputs to your electronically connected/multiplexed bit-D-Latches [D0][D1][D2][D3] and a parallel output multiplexer to [parallel output port] that has 4 lines output to output multiplexer - so mid-summary:
    you have your 4 bits mux-ed eighter FW direction or BW direction
    you have your "outer bits" bi-MUX-ed for internal recycle or just direction wise serial data I/O
    you can MUX your I/O and serially and in parallel in between multiple:
    • serial input buses
    • serial output buses
    • parallel input buses
    • parallel output buses
    where :
    • a serial I/O can be another 4-bit (serial shift) register - as well and any other 1-bit wide I/O
    • a parallel I/O can be another 4-bit (serial shift) register - as well and any other 4-bit wide I/O
    . . . it's far not the whole node network that can be set up and electronically reconfigured . . .
     
    vead likes this.
  11. ci139

    Member

    Jul 11, 2016
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