Shift register Timing diagram

Discussion in 'Homework Help' started by *.*.*AnUm*.*.*, Jul 11, 2015.

  1. *.*.*AnUm*.*.*

    Thread Starter New Member

    Apr 21, 2015
    16
    0
    Hi,

    upload_2015-7-11_12-27-38.png

    See this snap shot this was video lecture recorded by instructor but he did not explain this right shift register timing diagram well. Please explain it, how this diagram works ?

    Thanks.
     
  2. WBahn

    Moderator

    Mar 31, 2012
    17,757
    4,800
    What is it that you are having trouble with in regards to the diagram?

    At the rising edge of the clock, Q_n takes on the value that Q_(n-1) had prior to the clock edge, except for Q_0 which takes on the value of the Data input.
     
  3. *.*.*AnUm*.*.*

    Thread Starter New Member

    Apr 21, 2015
    16
    0
    I got your point,

    Thanks :)
     
  4. *.*.*AnUm*.*.*

    Thread Starter New Member

    Apr 21, 2015
    16
    0
    But I have one more question:

    Practically where we use 4-bit right shift register ?
     
  5. ericgibbs

    AAC Fanatic!

    Jan 29, 2010
    2,503
    380
  6. *.*.*AnUm*.*.*

    Thread Starter New Member

    Apr 21, 2015
    16
    0
    hi,

    Thanks, this helped me :)
     
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