I am really struggling with the following question that is in a mock exam that I am revising. The marks are after each question.
Four of SN7474 D-Type, positive edge triggered flip-flips with preset and clear are to be used with other logic gates to design a 4-bit serial to parallel and parallel to serial converter.
Preset and clear inputs take precedence over other inputs. They are both active negative signals. If they are held low simultaneously the results are unpredictable when they return to the high state.
a) Draw the circuit Diagram of the 4-bit Serial Register using the 7474 described above and Label all inputs and outputs. [4]
b) If the serial bit stream “0101” is clocked into the device using 4 clock pulses , what are the contents of the register after the fourth clock pulse? [2]
c) Add some logic gates to provide a 4 bit parallel input under the control of a serial/parallel load signal. Label all inputs and outputs. [4]
d) If the hexadecimal number, $4, was loaded into the register from the parallel input, draw the serial out waveform if four clock pulses are then applied. [2]
e) It is required to store the data when loaded with the parallel load signal by inhibiting the clock with a separate signal called the Seial/Parallel Function Signal. Add logic gates to achieve this and explain why it may be advantageous for the Parallel load signal to be a pulse and not a state. [4]
f) With the current design, any Parallel data loaded and shifted out of the register is lost. It is required that this data is retained, if so required. Using a switch, add additional logic gates to provide this function. [2]
g) A read function is required to enable the Serial/parallel register data to be placed onto a 4 bit bus command. Add additional logic to do this. [2]
I have only managed to answer part a and b up to now. Please click on the link to see them: My Answers So far!
Any ideas for the remaining questions?? Any help would be much appreciated
Four of SN7474 D-Type, positive edge triggered flip-flips with preset and clear are to be used with other logic gates to design a 4-bit serial to parallel and parallel to serial converter.
Preset and clear inputs take precedence over other inputs. They are both active negative signals. If they are held low simultaneously the results are unpredictable when they return to the high state.
a) Draw the circuit Diagram of the 4-bit Serial Register using the 7474 described above and Label all inputs and outputs. [4]
b) If the serial bit stream “0101” is clocked into the device using 4 clock pulses , what are the contents of the register after the fourth clock pulse? [2]
c) Add some logic gates to provide a 4 bit parallel input under the control of a serial/parallel load signal. Label all inputs and outputs. [4]
d) If the hexadecimal number, $4, was loaded into the register from the parallel input, draw the serial out waveform if four clock pulses are then applied. [2]
e) It is required to store the data when loaded with the parallel load signal by inhibiting the clock with a separate signal called the Seial/Parallel Function Signal. Add logic gates to achieve this and explain why it may be advantageous for the Parallel load signal to be a pulse and not a state. [4]
f) With the current design, any Parallel data loaded and shifted out of the register is lost. It is required that this data is retained, if so required. Using a switch, add additional logic gates to provide this function. [2]
g) A read function is required to enable the Serial/parallel register data to be placed onto a 4 bit bus command. Add additional logic to do this. [2]
I have only managed to answer part a and b up to now. Please click on the link to see them: My Answers So far!
Any ideas for the remaining questions?? Any help would be much appreciated
