Shift register problem

Discussion in 'Homework Help' started by galalog, Jan 12, 2012.

  1. galalog

    Thread Starter New Member

    Jan 12, 2012
    show the put put wave form for a serial in serial out right shift register for specific dara input and clock signal . required to shift 10 bits out of shift register. assume that register initially contains all 1s.and please draw the timing diagram.

  2. galalog

    Thread Starter New Member

    Jan 12, 2012
    sir ,
    I post a problem to you about the digital logic and design under the title of shift register please immediately feed back because i have have only 12 hours left to solve this problem which i cannot understand , please in this regard help me quickly
  3. Wendy


    Mar 24, 2008
    Welcome to AAC!

    A thread belongs to the OP (original poster). Trying to take over someone elses thread is called hijacking, which is not allowed at All About Circuits. I have therefore given you a thread of your very own.

    This was split from

    You gave absolutely no information about your problem. I suspect you are not going to get what you need. The more information you give (schematics, setup, etc) the more likely someone will step in and try to help.
  4. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
    Look at the datasheet for the shift register, every time the clock changes, whatever is on the data line is shifted in, and the rightmost bit is shifted out (to next shift register if connected, or discarded otherwise).

    The datasheet has a timing diagram.

    What part are you having problems with? It's usually best to not wait until the last minute to do homework.
  5. MrCarlos

    Active Member

    Jan 2, 2010