Hi guys... new here

I have a problem with the following and hope all the gurus here can help me out on this


Consider a transmission system using Cyclic Redundancy Check (CRC) technique with a
generator polynomial​

​

​

​

10101. The receiver receives the following bit pattern:​

100111011000.
​

(a) Draw a digital logic circuit for a shift register implementation of CRC.
[8 marks]



(b) Use the logic to evaluate the received bit pattern to see whether the bit pattern
is error-free.​

[12 marks]


thank!

 

There are a number of very good articles on the Internet that present a solution that uses gates. Here is a pretty thorough article on CRC that covers the subject.

hgmjr

 

thanks for the link hgmjr!


so base on that article 10101 = 1*x0 + 0*x1 + 1*x2 + 0*x3 +1*x4

therefore = 1 + x2 + x4

but is the circuit like this?


A<---B + C<---D +

 

Please help to see if this is correct becoz the 12 mark question is ok for me... juz need to get the circuit right... pls?

 

Go ahead and take a stab at drawing up the CRC circuit and post it here. We can then make suggestions on what you need to adjust should a correction be needed.

hgmjr

 

Did you use the "MANAGE ATTACHMENTS" button to attach your diagram?

hgmjr

 

here you go...

 

I would imagine that you would need 5 stages rather that just 4, since there are five bits in your CRC term.

hgmjr

 

i look at my coure notes and they only have A B C D for 5 bit 11001

and this is how they drew it


can you kindly enlighten me directly??... i am really confused now

thanks...

 

I stand corrected.

You wrote the correct equation in your earlier post.

I am used to the flow shown like the article that I linked you to earlier.

One thing for sure, your vertical arrows should be pointing into the circled + signs rather than the flip/flops.

hgmjr