Hi guys... new here I have a problem with the following and hope all the gurus here can help me out on this Consider a transmission system using Cyclic Redundancy Check (CRC) technique with a generator polynomial 10101. The receiver receives the following bit pattern: 100111011000. (a) Draw a digital logic circuit for a shift register implementation of CRC. [8 marks] (b) Use the logic to evaluate the received bit pattern to see whether the bit pattern is error-free.[12 marks] thank!