DIGI book chapter 12 SHIFT REGISTERS part 12.2 serial-in/serial-out shift register
The graphic titled "Serial-in, serial-out shift register using type "JK" storage elements" has a NOT gate in series with the K input. This results in a low q on Qa after the clock when the data input is pulled high. This shift register is shifting it's opposite; 1 on the input equals a 0 on the output. That 0 on the input of the following storage element after the first clock cycle equates to a 1 on it's output by the second clock cycle and so on. The next graphic after that, showing clock, data in, Qa, Qb and Qc says, "...stage A sees a logic 0, which is clocked to QA where it remains until time t2." which is incorrect. The graphics will need revision as well as the explanations that follow. I assume you can make the correct changes, but if you need further explanation or help, let me know.

 

Inverting J and feeding it into K of a J-K flip-flop turns it into a D-type flip-flop.

 

A D-type flip flop, according to the multivibrator section chapter 10, does not have it's outputs fed back to the the gate and shows a NOT gate in series with the S input. A high for the D-latch will pull low on the S input which will result in a high Q. The J/K flip flop on the other hand has its outputs fed back to it's input gate and as far as chapter 10 is concerned does not inherently have an inverter on either it's J or K inputs. The graphic shows one inverter on the first storage element, but not on any of the following so I assume they are not there by referring back to chapter 10 where J/K flip flops are introduced. Even if they were, a high towards the J input insures a low on the K input. If Q was high to begin with then the J input goes high, pulling it's output, Q, low. Q will stay low as long as the input is pulled high for each clock signal. If there were an inverter (not shown) on the K inputs of the following storage element it would result in both it's J and K inputs being pulled low by the second clock signal, assuming the first input was high for the first clock signal which would result it's output being low Q and high not-Q. At that point the second flip flop would have 0 on both it's inputs latching it to it's previous state and most importantly not resulting in a shift of the bit.

 

Without an inverter on the J input, Q will be inverted. The subsequent J/K flip flops will continue inverting there inputs to outputs with every clock cycle.

 

I cannot decode what you are saying. It is too long for me to follow.

I see nothing wrong with the circuit as shown:

 

For the diagram with JK flip flop storage elements let's assume all the Q outputs are preset to 0 and not-Q to 1. All of the inputs J will be pulled low and K pulled high.

If 'data in' is pulled high then J on the first flip flop pulls high and K pulls low?

The thing to remember is that with a JK flip flop the output Q is fed back to a 3 input AND gate with the J input and the clock. The same is done for the K input.


http://www.allaboutcircuits.com/vol_4/chpt_10/6.html

Wih Q previously being 0 that means the gate to the J input is off for the first clock pulse regardless of the input. With Q being pulled low, one of the inputs to it's AND gate are pulled low. With that AND gate pulled low by the output of Q, J will be receiving a low signal for the next clock. With the K input already receiving a low, both inputs will be pulled low and the effect will be a 'latch' on it outputs instead of a shift. http://www.allaboutcircuits.com/vol_4/chpt_10/2.html

All subsequent shifts from J to Q and K to not-Q with be inverted with every clock pulse.

 

I may wire this up to test it, but it looks OK to me too. At this moment I'll call it undetermined until verified or rejected.