SF amplifier

Discussion in 'Homework Help' started by darylsingh, Jul 21, 2011.

  1. darylsingh

    Thread Starter New Member

    Jul 10, 2011
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    Can someone please help me get started, I'm not sure where to start from with this homework problem. I am to design an SF amplifier using an n-channel JFET for a current gain of 100 and an input resistance of 500k ohms. The load is 2k ohms and VDD is 10V. And I'm given the following parameters to select my Q-point: VDSQ = 8V, IDQ = 5mA, VGSQ = -1V, and gm = 1/4mΩ.
    Can someone please help..Thanks
     
  2. darylsingh

    Thread Starter New Member

    Jul 10, 2011
    15
    0
    Can someone please help, I'm not looking for answers from anyone. I just need to know where to start from and possibly some equations to use because I'm not sure if the same equations are used from CS amps. Please Help
     
  3. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    1,097
    Do you know that current gain for JFET is equal to infinity.
    And the first thing you should do is determine the JFET parameters Idss; and Vp form a given gm.
    And "SF" = source follower ??
     
  4. darylsingh

    Thread Starter New Member

    Jul 10, 2011
    15
    0
    Thanks for the info, my book is telling me to design with the current gain of 100 and then I see some formulas given for it as well; Ai=vout/Rload*RG/vin = (Av)(RG/Rload) = RS||Rload/(RS||Rload)+(1/gm)*(RG/Rload)=RS/(RS+Rload)*RG/((RS||Rload)+(1/gm)). This is what kind of confuses me. You said that current gain is infinite in a SF amp, then why these formulas?:confused: And then, to find Idss and Vp, do i use the same formulas as i did for a CS amp, which were, Idss=Idq*2 and Vp=Vgsq/.3?

    Thanks for all the help, I really appreciate it.
     
  5. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    The FET itself is essentially a voltage-controlled device, and is not usually thought of as having a particular current gain. The gain would be enormous, but as gate leakage is quite unpredictable, and in the case of a JFET quite non-linear, the gain level would be ill-defined.

    A FET amplifier can have its current gain fixed at a lower and more predictable level by having a resistively terminated input, which is what your formulae refer to. Some people may however find this sort of problem a bit artificial, as the current gain is not subject to the well-defined inherent limitation found in a BJT amplifier.
     
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