Setting an IC to a known state at power on

Discussion in 'General Electronics Chat' started by jaygatsby, Dec 12, 2011.

  1. jaygatsby

    Thread Starter New Member

    Nov 23, 2011
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    A few times I've heard, 'random data is in this register', or other IC. Is there a standard way to clear flipflops and things like that when a circuit is turned on? For instance if I always want a counter to begin at 0?
     
  2. crutschow

    Expert

    Mar 14, 2008
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    Typically a simple RC delay circuit is used to apply a signal to the Reset inputs at power up. The C goes from V+ to the Reset inputs and the resistor goes from the Reset inputs to ground. The RC time-constant should probably be at least twice as long as it takes the power supply to power up.
     
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  3. sheldons

    Active Member

    Oct 26, 2011
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    just as an example heres two reset circuits-on gives a hi going reset the other a low going reset
     
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  4. crutschow

    Expert

    Mar 14, 2008
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    Just to note that those reset circuits only work with a high impedance reset input such as CMOS or most microprocessors provide. It has to be a lower impedance to reset TTL bipolar digital circuits.
     
  5. JMac3108

    Active Member

    Aug 16, 2010
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    Be careful with this type of power-on reset circuit. Check the datasheet for the maximum input transition time on any chip you plan to drive this way. Its usually OK with reset lines. However, the attached file shows the specs for a 74HC00 CMOS NAND gate, and it is not OK. The datasheet specifies a maximum transition time for an input of 500ns. This means that your low-to-high or high-to-low transition can't take any longer than 500ns.

    If you have a CMOS part with inputs like this, and you want to initialize it to a known state at startup, try one of these methods.

    (1) Use the RC reset as described in this thread but buffer it with a schmidtt trigger gate.

    (2) Use a power-on-reset chip, also called a uP supervisor IC.
     
  6. Wendy

    Moderator

    Mar 24, 2008
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    Just curious, what do you think will happen if the transition takes longer?
     
  7. JMac3108

    Active Member

    Aug 16, 2010
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    I'm not 100% sure but the problem has to do with staying too long in the transition region between a high and a low. You can get a large current spike if both CMOS transistors are on at the same time. I suppose its also possible that the IC could oscillate or latch-up.

    I've never looked up the exact consequence of doing this - I just put it in the category of "don't do that" :)

    Maybe someone has time to look up details on this and share?
     
  8. ErnieM

    AAC Fanatic!

    Apr 24, 2011
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    Microchip makes a line of "Microcontroller Supervisory Circuit" chips that provide a wide varieity of voltage sense points and output styles that could be ideal for applications such as this.

    For under 50 cents you get a 3 terminal device you connect to the power rails, and the last pin is an output, either push pull or open collector (drain actually), active hi or low. These things check the power supply and once valid give a digital pulse of a short known duration with sharp edges.

    With so may options one of these should fit your needs.
     
  9. JMac3108

    Active Member

    Aug 16, 2010
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    Dallas/Maxim make these too. And maybe National? They're great parts.
     
  10. Audioguru

    New Member

    Dec 20, 2007
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    Texas Instruments show the typical and minimum output current from all their ordinary CD4xxx Cmos ICs and for their SN74HCxxxx high speed Cmos ICs.
    The max allowed continuous output current from one SN74HCxxx output is 25mA. The max output from a package is 50mA.

    The typical output current from a 74HCxxx IC output is about 42mA when the output voltage is half the supply voltage. Then each output transistor heats with 2.5V x 42mA= 105mW. Current more than 25mA will cause each output transistor to dissipate more than 62.5mW when reduced duration (fast transition)keeps it from burning up.
     
  11. sheldons

    Active Member

    Oct 26, 2011
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    heres some other reset schematics for use...depending on application the timing can be changed to suit but they do work well
     
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  12. Audioguru

    New Member

    Dec 20, 2007
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    In the left circuit the capacitor is discharged by leakage currents at rest. When power is applied the capacitor takes time to charge by R1 so the transistor is turned off and its collector voltage is a logic high to reset a counter (if the counter needs a logic high for a reset).

    In the right circuit the transistor and resistors discharge the capacitor at rest.
    When power is applied the transistor is instantly turned on and its output produces a logic low as a reset (for guess what?).
     
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