Serial to Parallel Converter

Discussion in 'The Projects Forum' started by MrL, Oct 21, 2009.

  1. MrL

    Thread Starter Member

    Oct 21, 2009
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    Hi,

    I've been doing Digital Design for just under a year now, and figured this would be a good place to sign up.

    I am working on a project in which i am requird to have a data reciever which converts asynchronus serial data, into a parallel 4 bit output. The data will contain a start bit of logic 0, then the 4 data bits, followed by the stop bit of logic 1. A 'handshaking' protocol is also required from the reciever to the deivce which will use the data.

    Currently, my design consists of a shift register made of D type flip-flops, which are all connected to a clock and a reset. I also have a clock divider made of D type flip-flops.

    I was wondering if anyone could advise me as to how i can implement the stop/start bit into the design? Also, how would i go about the handshaking protocal?

    Any help would be much appreciated.
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
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  3. MikeML

    AAC Fanatic!

    Oct 2, 2009
    5,450
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    The OP is asking how to implement a UART; not how to convert logic levels to the RS232 voltage levels, which is what a MAX232 does.

    Read this, and look up the 8250 chip and its derivatives. This one chip does everything you need, including Start/Stop detection, serial/parallel conversion, parity checking, clock recovery, etc. Why build all this if you can buy a single cheap chip that does it all.

    If the 8250 et,al doesn't do your weird 4 bit (why invent a new standard?) protocol, then use an 8 pin PIC ($0.50).
     
  4. spacewrench

    Member

    Oct 5, 2009
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    Wait, what? The MAX232 I know is an RS232-to-TTL level shifter. I don't think it does serial-parallel, and I'm pretty sure it doesn't do handshaking.

    The easy way to do this would be with a microcontroller (pretty much any one will work). I've been using Atmel ATmega328Ps recently, they come in a 28-pin narrow DIP for easy breadboarding, and have plenty of RAM, Flash and etc. for easy-to-moderate projects.

    If you have to do it with flip flops, you could have the start bit cause a clock (at the serial rate) to start ticking. On every falling (or rising, your choice) edge, you shift the serial data through your flip flops. When the start bit falls out the top FF, it stops the clock. Then you read the 4 bits off the Q outputs.

    You could use the input-clock-stopping signal to start a second set of flip-flops going, which send out the handshake reply.

    In fact, you could have the clock run continuously and use the top bit of the input S/R to control whether the input or output S/R gets the clock signal. (The problem with that is, you really need to have the clock start synchronously with the falling edge of the start bit, so you can sample the signal in the middle of each bit time.)
     
  5. t06afre

    AAC Fanatic!

    May 11, 2009
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    I have never used it my self, but it is method called "Bit banging" If you google "bit banging uart" you will get some useful hints. Then implement this in PIC micro. Before you to deep into "bit banging" you should know that, as I understand not a very fast method.
     
  6. MrL

    Thread Starter Member

    Oct 21, 2009
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    Thank for the help guys, i'll let you know how i get on. Also, i'm required to build this from basic logic gates/flip-flops.
     
  7. davebee

    Well-Known Member

    Oct 22, 2008
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    Here's what bit-banging code would look like:

    wait for start bit
    pause 1.5 bit times
    read data level and shift onto result
    pause 1 bit time
    read data level and shift onto result
    pause 1 bit time
    read data level and shift onto result
    pause 1 bit time
    read data level and shift onto result
    pause 1 bit time (stop bit)
    set handshaking bit
    wait for handshaking response
    clear handshaking bit
    go back to waiting for the next start bit

    Doing it with logic gates will be harder, but maybe this code description will help as a guide of what to do.

    I've made logic circuits in the past that did complicated tasks by clocking a counter, connecting the counter output bits to a 3-to-8 decoder and using the decoder output lines to enable different tasks in the correct sequence. Maybe a technique like that could help with this project.
     
  8. MrL

    Thread Starter Member

    Oct 21, 2009
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    Hi again,

    I've been thinking long and hard about this and still have a few problems. Here is my design so far (done on paint quickly, sorry for the mess):

    http://img40.imageshack.us/img40/2478/roughsketch1.jpg

    Basically so far, i have a clock divider, with the serial data going at a rate of that of the clock/16. The shift register is negative edge triggered, and uses clock/8 as it's clock. Therefore, as shown in the diagram, the data will shift half way along the time period of the serial data. I think this conecept is correct so far?

    I'm now having trouble with implementing the stop/start logic. The data packet will contain a '0' logic start bit, then the 4 data bits, followed by a '1' logic stop bit. I came up with a few ideas which i aren't too sure on. I was thinking i could implement some kind of logic gates to the T input on my gates in the clock divider, which control the clock stopping/starting. Or I could implement a digital counter connected to the same clock as the serial data, and then at certain counts (ie. logic 5: 0101) i'd know i'd need to stop the data (this is just an example, and not accurate to this case.

    Could anyone help me in this area please?

    Thanks.
     
  9. MrL

    Thread Starter Member

    Oct 21, 2009
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    I also forgot to add, when the data packet has been recieved and available for an external system, a data available output must be asserted active low by the reciever. It is held at 0 until the data is no longer available, or has been read. When the data is read, it will apply a 0 logic to a data read input on the reciever. If another set of data is recieved before the current one has been dealt with, the reciever must assert an active low data run output, and this output is held active until data read is asserted by the external system.
     
  10. MrL

    Thread Starter Member

    Oct 21, 2009
    46
    0
    Would anyone be able to help please?
     
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