# Serial Comparator

Discussion in 'Homework Help' started by mrjackd, Sep 4, 2005.

1. ### mrjackd Thread Starter New Member

Sep 4, 2005
4
0
what i need:

the comparisons

M > N
M = N
M < N

an input A which designates whether or not the bits come in least significant bit first or most significant bit first.

so

INPUT | OUTPUT

M | M > N

N | M = N

A | M < N

Clock |

operating on a bit by bit basis.

the correct comparison needs to be decided after n(= 4) clock pulses.

I would really like some help with this in the form of anything you can give me, id really like the boolean functions required.

If anyone could supply me with the whole schematic, moore diagram and characteristic table then i'd pay you £15 - £20 by PayPal depending on how impressed i was with the design. I will very much appreciate any help given though.

Thank you.

2. ### pebe AAC Fanatic!

Oct 11, 2004
628
3
I've read your post several times and I still cannot figure out what you are trying to do. It needs a little more detail.

Is this a 4bit stream you are talking about?

You want to know whether it's being sent LSB or MSB first? If so, what is is to be compared with?

In a μC or a PC or using discretes?

3. ### mrjackd Thread Starter New Member

Sep 4, 2005
4
0

M is a bit stream and so is N. There will be a stream of 4 bits coming in assumed to be synchronised with each other through input stream M and N, it will be required that the comparator circuit decides after 4 clock pulses which stream, M or N is greater than, less than or equal to. The input A will tell the circuit how to expect the stream, either least significant bit first or most significant bit first.

Most significant bit is the easiest as it can latch on the first inequality that it finds, for least significant bit however the logic scheme will have to be capable of reversing an early decision.

Is that any clearer?

4. ### mrjackd Thread Starter New Member

Sep 4, 2005
4
0
Basically i need a Moore, ASM or Mealy model of the serial comparator.

The assignment of a unique binary code to each state in the design (the initial state being 00)

The derivation of a characteristic table describing the state behaviour of the design

The derivation of the boolean logic functions describing next-state and sate output combinational logic

The derivation of the schematic diagram for the FSM comprising inputs (including the clock), outputs, state-register, next state logic and state output logic.

Like i say, for anybody that can do this easy then this is a quick way for you to make some money. I will pay, trust me, id be so gratefull it would be unbelievable seeing as i'll be up all night doing this tonight otherwise.

5. ### mrjackd Thread Starter New Member

Sep 4, 2005
4
0
Finished it myself now, not really simplified thought.