Well, even if the current is only momentary, you'll still be subjecting the resistors you've been considering to enough power to turn them into light bulbs for a brief moment. You might get away with a momentary load of 3x to 5x of the power rating, but most DIP resistors are rated around 200mW, and 60w is 300x that.

And as I also mentioned, DIP/SIP resistors won't be useable due to the HV, unless you can find some components with a minimum of 0.17" pin spacing and 3.5kV rating. They might be out there, but will likely be pretty scarce.

The HRV37 series are 1/2 W 3.5kV rated, which is actually a bit marginal for the voltage rating. Vishay also makes the HRV68 series which are 1W 10kV rated. I haven't looked for a source, but if you want this STE to be really reliable, those would be a better option.

Connecting the STE to the DUT is another issue. Can the resistors, and preferably the NPN Darlington arrays be integrated into the DUT? If not, you're going to have a connector problem, as you'll need that minimum .17" between pins. Either way, it's going to require a good bit of real estate. Conformal coat will help out a great deal in reducing the footprint, as then you won't have to worry so much about air gaps. However, the working voltage and power ratings will still be a concern.

You mention that the 3kv flash will be brief - exactly how brief?
My concern is the time required for latching the shift registers. The data inputs need to stabilize, then the parallel load/shift needs to go high, and then P/S\ needs to fall to latch in the data. Up until now, I'd made the assumption that the input would remain high until the Stamp pulled the line low. This is obviously no longer the case, so give me some timing info.

 

The flash time is close to 1ms. Basically the hypot protects itself from the return voltage so as soon as it flashes it turns off all voltages being produced.

 

Oh, BTW - is this STE a deliverable item, and if so, are you bound to using the PPSL?

Meanwhile, looking for suitable Schottky diodes over the weekend, I found BAT54A's; they're a KAK Schottky pair in an SOT23 package. Mouser carries them for as little as $0.03/each in the quantities you'd need. When If=1mA, Vf=320mv. Nice.

 

As of yet, no it's not deliverable, and no, I'm not bound to using just those parts. I really liked the isolation that the optoisolators provided though.

nice find by the way.

 

I appreciate the motivation for isolation. But, trying to get enough current to consistently fire an optocoupler's LED from a 3kV source without using a huge resistor is going to be a challenge. If you're bound and determined to use an optocoupler, you could still do so if you used a source-type noninverting NPN/PNP driver.

Using clamping diodes on the input would be the "safety net" in case the base/emitter junction opened up. That's one of the reasons why I recommended the UDN2981's; they have clamping diodes on the outputs. With a 33M resistor between the input and the 3kV source, the clamp diodes could sink the <1mA current without even getting near to breaking a sweat.

 

so you were thinking something like this then? (and instead of the resistor package, they would be free standing, high power resistors.)

 

Actually, that's similar to an earlier version of the board I was working up.

However, MTBF of a board with that many dual diodes on it would be a problem. So, I went to a motherboard/daughterboard configuration. See the attached.

The DB25 connectors carry Vdd, Vss(gnd), 22 Y-axis signal paths and 1 each X-axis signal paths. For the monitoring of 400 points, you would need 18 full daughterboards, and one additional daughterboard with 4 channels populated. If 24 complete daughterboards were installed, you would have the capacity to trap 550 events.

The DB9 connectors are for diagnostics. Six are address lines, one clock line, Vdd and Vss. As of yet, I haven't added a binary counter for generating the board addressing.

The common-anode diodes are on the daughterboards, driven by three 8-input source arrays. Connections to the DUT haven't been put in yet, as that seems to be up in the air as of yet. The remainder of the ICs and the 6-position DIP switch deal with address decoding and clocking the three 4017 Johnson counters for the purpose of diagnostics. However, it may be a better idea to leave diagnostics completely separate from the daughterboard; ie: a plug-in module.

 

yeah I pretty much figured the daughter boards were implied. as for the connections to the DUT, they are being wired in where the simulated short is being represented. So essentially from where the Resistors are on the front side of the schematic to the 3KV. This way if there is an arc then it will complete the circuit and therefore opening the transistor gate.

 

Just thought of this, wouldn't just using a straight npn work with attached diode on the emitter going into the x-y array, +5V on the collector, and the input from the DUT going to the base through a resistor-diode series.

This would provide a lot less impedance, and still do the job. Assuming we can come up with a resistor that will work from that 3kV.

 

Yes, that idea will work!

However, there needs to be clamping diodes on the base of the transistor to prevent the base from becoming higher than a volt over Vcc, or less than -1v.

If Vbe becomes sufficiently negative, it will exceed the emitter breakdown voltage and fry the transistor. This will happen very quickly if there is any inductance in the "big" resistor between the 3kV and the transistor's base, or even if there is a run of significant length from the resistor to the base - that would result in parasitic inductance.

If Vb becomes more than 6v, the transistor has opened up, thus there would be no load on the low side of the resistor; causing the voltage to rise very rapidly to the 3kV potential or until a flashover occurs, whichever comes first. In a densely-packed PCB, my bets are on the flashover.

This is a case where an ounce of prevention (and a couple of diodes) is worth far more than 10lbs of cure.

Having some 5.6v Zener diodes between Vdd and ground/Vss would provide a backup safety net in case either the Vdd or Vss/ground lines were damaged.

 

Very true!!!! I would hate to see the transistor be the fuse in this whole operation, cuz you know once that goes it's just a chain of destruction to follow.

 

Absolutely.

When you're dealing with voltages that high, you'd better have a couple of fallback positions to take the brunt. Otherwise, it'll eat up the rest of the circuit in a big hurry.

After running some more simulations, I'm re-thinking the values for the termination resistors and latching mechanism.

Initially (when I whipped up the 1st schematic) I set up the termination resistor values on the assumption that the trigger signal (applied across the base of the transistor) would be available indefinitely, and the uC (the BS2px24) could take it's sweet time to pull the P/S\ low to latch the signals.

Frankly, I don't know if the BS2px24 can loop tightly enough to poll for a 1mS pulse, detect it, change the pin to an output, assert it low and latch the data before it goes away. I don't have a BS2px24 to experiment with. However, you could try it with the one you have.

This is one of those projects where you're going to have to test everything before you try to formalize it.

 

Yeah, I've been trying for the past couple of days to figure out the programming of the parallax chip. Sadly, I'm still pretty new to pbasic, and even though it's extremely basic I'm used to programming such as C+. So I'm still in the learning process.

What if we were to put a couple of latches on the output of the shift registers?

 

Well, the shift registers themselves are latches!

I noticed that you had your P/S\ inputs wired differently than I did.

The way I wired them in my diagram, a "hit" anywhere in the network would cause ALL of the P/S\ inputs to go high, along with P11 on the BS2px24, which would be set to input.

When the BS2px24 "saw" the logic 1 on that line, it would then need to set the pin to output, and assert a logic low, thus latching the data in the shift registers.

Have a look at the attached. It's a simulation of just one X-axis and one Y-axis shift register inputs, basically according to how I had 'em wired up. You'll note that the P/S\ inputs have parallel current paths; that's because all the P/S\ inputs are connected together in my schematic. C1 and C2 aren't physical components; that's just a SWAG for the parasitic capacitance in the circuit; it's likely a bit on the low side.

Note the green trace on the simulated O-scope. It reaches 4v, so that's enough to be considered a logic "1". However, it continues to stay high after the data inputs have fallen back to a logic low level.

Basically, the current P/S\ input needs to trigger a 1-shot MV to latch in the data. The 1-shot could also charge a cap through a diode to put a logic 1 on the input to the Stamp.

I'll noodle on this for a bit.

 

Yeah, I saw your wiring but I didn't really notice a change in the simulations.

 

OK, here's the solution to the latch timing problem.

See the attached.
The P/S\ line was cut.

R3 and C4 make up an RC network to give a slight time delay to the input strobe (the 1mS pulse) so that data at the Px inputs of the shift registers has time to stabilize. When the voltage on C4 has increased to 2/3 Vdd, the output of U3A, a quad Schmitt-trigger NAND gate, drops low, latching the data in the registers and enabling data shift mode.

Meanwhile, C4 is charged sufficiently to hold a logic high level for an extended period of time; at least 30mS. That time can be increased by increasing the value of R4. R4 is present to prevent the dreaded "floating input" condition.

This gives the BS2px24 an extended amount of time to recognize the logic 1 on it's input pin.

As soon as the Stamp sees the 1, it needs to:
1) Change the pin to an output.
2) Continue asserting a logic 1 to keep the shift registers latched.
3) SHIFTIN the data from the X-registers.
4) SHIFTIN the data from the Y-registers.
5) Display/log the results.
6) Change the pin to a logic low, and leave it there for a period of time (1mS will be more than enough) to discharge the capacitor.
7) Change the pin back to input, and begin polling again.

While writing this, I realized that the Stamp pin needs a 270 Ohm resistor between it and the 1uF cap to limit current to < 20mA during the discharge cycle. It's been added to my simulation.