Hi all,

I have been reading the AN attached, and if I understand correctly, SCR latchup in CMOS ICs is only a risk when a P-channel and an N-channel find themselves in close proximity to each other.

Is this a common scenario in most all CMOS ICs or just when you have a push pull output stage?

Regards,

 

It is an issue with many logic/switch ICs, both MOSFET and transistor based.

Follow the app notes for particularly sensitive devices, usually mentioned in datasheets or app notes.

Use 0.1uF decoupling caps on all ICs to help stabilize power supply.
Avoid running/having inputs near or outside minimum and maximum voltages.
If possible, apply power to ICs before applying input signals.

 

I am quite familiar with practices to avoid it, just not overly familiar at being able to identify susceptible candidates.

Can you elaborate on your first statement? "It is an issue with many logic/switch ICs, both MOSFET and transistor based. "

Is it only when the logic has and P and N channel adjacent pairs? So this can also be a problem for TTL logic? Is it the exact same phenomenon?

Regards

 

The condition on silicon occurs most often in push/pull outputs, but other cases arise as well, most are now avoided through proper mask design.

This app note shows a few IC layouts that are susceptible.
http://www.analog.com/library/analogDialogue/archives/35-05/latchup/

 

Just assume that all devices are susceptible. There has been a lot of progress in the last 30 years in the area of reducing susceptibility, but even with those remedies in place, chips can still latch up given enough current in the wrong place.