Hi everyone,
I'm not sure if most people know or not, but most of my postings are related to a single project that I have been working on. I wanted to see if someone can suggest a bypass capacitor to use for my circuit. The OUT1 and OUT2 go to a 0.8 Ohm 50mH inductance. It is being PWM switched at around 50KHz, but I may go up to 100KHz. The on-resistance of the FETs in the bridge are 0.15 Ohms nominal.
The sense resistors each go into their own differential low-pass filters with a cutoff of about 15KHz. I'm planning to sample the ADC at 30KHz. These differential amplifiers go directly into an instrumentation amplifier with selectable gain between 5 and 10. These should provide the actual current value in volts because I choose a 0.1 Ohm sense resistor. The gain of 5 is when the bridge is in slow-decay mode, which I would normally get twice the current shown. I'm using a simple logic circuit within the FPGA (not shown) to control this. I have supply filters on the opamps to reduce noise, I chose the cutoff to be around 10KHz, which is where the PSRR to frequency starts to really dip for both the instrumentation amp and the opamp. The TBD cap is a really small capacitance to eliminate the sense resistor spike when the h-bridge changes state.
Any red flags? Can someone make a suggestion? I'm going to check this over with a professor and it will be final lest anyone speaks from here.
Kindest regards,
Steve
I'm not sure if most people know or not, but most of my postings are related to a single project that I have been working on. I wanted to see if someone can suggest a bypass capacitor to use for my circuit. The OUT1 and OUT2 go to a 0.8 Ohm 50mH inductance. It is being PWM switched at around 50KHz, but I may go up to 100KHz. The on-resistance of the FETs in the bridge are 0.15 Ohms nominal.
The sense resistors each go into their own differential low-pass filters with a cutoff of about 15KHz. I'm planning to sample the ADC at 30KHz. These differential amplifiers go directly into an instrumentation amplifier with selectable gain between 5 and 10. These should provide the actual current value in volts because I choose a 0.1 Ohm sense resistor. The gain of 5 is when the bridge is in slow-decay mode, which I would normally get twice the current shown. I'm using a simple logic circuit within the FPGA (not shown) to control this. I have supply filters on the opamps to reduce noise, I chose the cutoff to be around 10KHz, which is where the PSRR to frequency starts to really dip for both the instrumentation amp and the opamp. The TBD cap is a really small capacitance to eliminate the sense resistor spike when the h-bridge changes state.
Any red flags? Can someone make a suggestion? I'm going to check this over with a professor and it will be final lest anyone speaks from here.
Kindest regards,
Steve