sampling event b/w clk domains

Discussion in 'Embedded Systems and Microcontrollers' started by tuborggg, Feb 23, 2009.

  1. tuborggg

    Thread Starter Active Member

    Jan 3, 2009
    I'd like to be able to get a signal from a fast clk to a slow clk.
    I know I can make the source signal keep its value for a bigger time -
    That's not what I want - I can't control on the original source signal, just the slow clk.
    What I thought of is putting the fast signal in the slow domain and 'locking' '1' when appears and releasing it only when sampled at the slow clk - but it's problematic due to timing issue....someone has a better idea?