Sample and Hold

Discussion in 'Homework Help' started by menewbie, Feb 28, 2006.

  1. menewbie

    Thread Starter Active Member

    Jan 31, 2006
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    Hi, I am designing a 3-bit dual-slope integrating ADC. The sample and hold circuit that I have designed operates well if the input voltage is positive. However, when the input voltage becomes negative, the lowest voltage that it can output is -0.5. Any idea how to solve this problem???
     
  2. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
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    It'd be easier if you could post your S/H schematic here.
     
  3. menewbie

    Thread Starter Active Member

    Jan 31, 2006
    34
    0
    Hi, n9352527. Thank you for your reply. I have attached two files that show the S/H amplifier. The attachment SH is the S/H amplifier on block level and SH1 is the S/H amplifeir shown in transistor level.
    (Gm is the transconductance amplifier)

    I think I know why the S/H amplifier doesnt work when the input voltage is negative. The output swing is limited by the Vss of the transconductance amplifier. In the transconductance amplifier that I have designed, the Vss is ground. Therefore the lowest output voltage is -Vthn. (Vthn is the threshold voltage of NMOS). I have tried to connect Vss to negative voltage supply, however, if I do that then the transconductance amplifier would not operate correctly. The only way to solve this problem is to change the design of the transconductance amplifier. Not sure if that is correct...
     
  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    You are right. You need to allow the amplifier output to swing negative to hold negative voltage. I don't see any other way around it except redesigning the amplifier. You might need to consider using transmission instead of pass gate for the switches depending on how you configure and control them.
     
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