Sample and Hold not working right

Discussion in 'The Projects Forum' started by sailmike, May 2, 2016.

  1. sailmike

    Thread Starter Member

    Nov 11, 2013
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    I am working on a sample and hold circuit that is not giving me the right output. The output should look like a staircase. I'm required to use discrete components for everything including the op-amps. The op-amps work fine. I need to understand the "big picture" on why this circuit isn't working right. I've attached a couple pictures of the circuit and output.

    Thanks,
    Mike
    Sample and Hold.jpg Sample and Hold Output 1.jpg
     
  2. ronv

    AAC Fanatic!

    Nov 12, 2008
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    You might want to post your .asc file.
     
  3. dl324

    Distinguished Member

    Mar 30, 2015
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    Is this homework?
     
  4. sailmike

    Thread Starter Member

    Nov 11, 2013
    143
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    I can't upload the file because it's too large. Is there another way?
     
  5. crutschow

    Expert

    Mar 14, 2008
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    That seems unusual.
    How large is the .asc file?
    Mine are typically only a few kB.
     
  6. sailmike

    Thread Starter Member

    Nov 11, 2013
    143
    3
    Just the .asc file and not the supporting files?

    I think the problem is the switch and the accompanying capacitance.
     
  7. sailmike

    Thread Starter Member

    Nov 11, 2013
    143
    3
    Nobody???

    I've lowered the switching speed to 750 kHz, but the output still doesn't look like a staircase. The sample and hold has to be able to accept input signals up to 100 kHz. It's my understanding that the switching speed should be about 5 times that input. I got a clock with a crystal working at 12 MHz and I cut that in half by running it through a D-flip-flop. This clock works and I don't want to start over with a new crystal. Since, it's an 8-bit ADC, 1/8 of 6 MHz is 750 kHz. I've attached a couple pics of the output shown on the scope. The switch I'm using was suggested by another forum member and it's DG212. This switch has an on resistance of 115 ohms and this seems kind of high. The capacitor is 0.01uF, which is suggested by a number of tutorials. I just need a better picture of what's happening and why the output doesn't look like a staircase. The second picture is as close up a picture as I could get. The input is in yellow and the output is in blue.

    SH Scope Pic 1.JPG SH Scope Pic 2.JPG
     
  8. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Can you post the .txt files defining the FET models?
     
  9. sailmike

    Thread Starter Member

    Nov 11, 2013
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    Yeah sure...
     
  10. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    You have 2 nodes labelled 'in', so they are shorted together. Likewise you have 2 shorted nodes labelled 'out'.
    Why do you have 2 FETS in parallel for the gating (sampling)?
     
  11. sailmike

    Thread Starter Member

    Nov 11, 2013
    143
    3
    Oh sorry, that's an older one. I'm using one MOSFET with a higher threshold voltage. I think the FET's in parallel are supposed to be opposites, NMOS and PMOS. I don't remember what that gate is called. The threshold voltage of the ALD212900 is 0.0 and I figured that it may not be turning off so I replaced it with one from the LTspice library with a threshold voltage of 1.0V. This didn't solve the problem. I'm still learning my way around LTspice. Someone helped me get the op-amp working. I just copied and pasted it to make the sample and hold.

    Shouldn't each op-amp have an input and output? How do you know they are shorted in the sim?
     
  12. sailmike

    Thread Starter Member

    Nov 11, 2013
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    I know the answer has to do with overshoot and settling time. I just don't remember how to minimize them.
     
  13. Alec_t

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    Sep 17, 2013
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    If you give two nodes the same label the simulator treats them as being the same point, electrically speaking.
     
  14. sailmike

    Thread Starter Member

    Nov 11, 2013
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    I'm not familiar enough with LTspice, but do I just change the name to in1 and out 1?
     
  15. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Yes, that works (but avoid the space character).
     
  16. sailmike

    Thread Starter Member

    Nov 11, 2013
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    How do I select it to change the name? I don't even know how it was added.
     
  17. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Right-click on the label (as you do to edit most things in LTspice).
     
  18. sailmike

    Thread Starter Member

    Nov 11, 2013
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    Ok, I think I got it. I'm still not getting the output I want. There seems to be too much overshoot and the settling time is too long. The switching transistor was picked based on the on resistance. How do I fix this?

    SH Simulation Circuit 2.jpg SH Simulation Output 1.jpg
     
  19. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    I suggest you forget about the amplifier sections for now and concentrate on simulating just the sample-and-hold section. Once you have that working to your satisfaction, bolt on the amps and see how that goes.
     
  20. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Two things to note about the S&H stage:
    1) To allow for the Vgs(thr) voltage of the sampling FET, Vg must go some volts above the voltage on the hold cap. The attached demo shows a plateau effect because Vg max = 5V only. Increasing it to, say, 10V would allow the cap voltage to rise to 5V.
    2) The hold cap loses charge to the gate-source capacitance of the FET when the FET turns off.
    S&H-demo.PNG
     
    Last edited: May 18, 2016
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