Sample and hold circuit

Discussion in 'General Electronics Chat' started by mentaaal, Feb 27, 2009.

1. mentaaal Thread Starter Senior Member

Oct 17, 2005
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Hey guys, I have a question relating to the use of the resistor in the attachment. The attachment depicts a basic sample and hold circuit.

According to the lecturer, the addition of the resistor is to allow the capacitor to discharge quickly. I just dont see how this occurs, or how this is a useful thing to do. A JFET's gate input controls the amount of current which can flow from the source to the drain. Does the addition of this resistor allow more current to flow from the drain to the source through the source?

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2. Ron H AAC Fanatic!

Apr 14, 2005
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The resistor allows Vgs to be exactly 0V then the control voltage is more positive than the input signal. This allows the maximum Ids that is possible without forward-biasing the gate junction, which is undesirable, as it would cause an error in the held voltage.
If the resistor is omitted, the intrinsic gate capacitance would charge up through the diode to approximately the negative peak control voltage, and then stay there when the control voltage goes positive, leaving the JFET off.
This ignores the diode capacitance, but it will generally be much less than gate capacitance.

3. mentaaal Thread Starter Senior Member

Oct 17, 2005
451
0
Thanks for the reply Ron. Ok i follow what you are saying in relation to the gate capacitance. I forgot all about that actually. Probably because I have literally never seen one outside of a text book. What i dont understand is how having the resistor between the gate and the drain makes the voltage between the gate and the source 0? Or maybe I have that wrong and you mean the resistor is between the gate and the source. But still how is that voltage 0?

4. Ron H AAC Fanatic!

Apr 14, 2005
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On many JFETs, source and drain are interchangeable. Even on the ones that aren't, I suspect the main difference when swapping drain and source will be a different amount of coupling of the gate drive pulse to the hold capacitor, due to the fact that Cgs and Cgd are different.
Regarding your question about the function of the resistor: Remember that, in order for voltage to exist across a resistor, current must flow through it. If you make the control voltage during the SAMPLE time more positive than the peak swing of the input signal, do you see a path for current through the resistor? The diode is reverse-based. Current can flow through the resistor and the gate to the hold capacitor if the input is more positive than the hold capacitor, but that will be momentary, because with zero or positive Vgs or Vgd, the FET will turn on, providing a low resistance path between the input to the output, which is what we want.
Of course, when the control voltage is in the HOLD mode (sufficiently negative), the diode will be forward-biased, and the gate voltage will be sufficent to turn the FET off.

5. mentaaal Thread Starter Senior Member

Oct 17, 2005
451
0
The problem I am having with this circuit is that our lecture explains the purpose of the resistor is to facilitate quicker discharge of the capacitor during the sample time if the input signal is smaller than the cap voltage. With that in mind does curent flow from the source (or drain as you rightly said) through to the gate and then the resistor to the other side of the transistor. Of course the curent can flow through the drain- source channel of the JFET as well. So does the resistor provide a parallel conductance during the sample time? Isnt this a bad idea as the gate is not designed to handle any larger currents than normal?

6. Ron H AAC Fanatic!

Apr 14, 2005
7,050
655
Well, I guess you could say it facilitates quicker discharge of the capacitor during the sample time if the input signal is smaller than the cap voltage. It also facilitates quicker charge of the capacitor during the sample time if the input signal is higher than the cap voltage. In fact, the circuit won't work without the resistor.
An N-channel JFET has two diode junctions, one from gate to source and one from gate to drain. the anodes of both are at the gate. When the input voltage is lower than the capacitor voltage, there is no current path through the resistor from the capacitor to the input, because the capacitor-to-gate junction is reverse-biased.
The resistor is not there to handle additional charge or discharge current. It is there to bias the gate at zero volts relative to the input when sampling, so the FET can be at minimum Rds.

7. mentaaal Thread Starter Senior Member

Oct 17, 2005
451
0
Cheers Ron. Thanks for all the help