Run more than one process in same VHDL code

Discussion in 'Programmer's Corner' started by dumindu89, Sep 13, 2012.

  1. dumindu89

    Thread Starter Member

    Oct 28, 2010
    113
    0
    I want to run more than one process in parallel in the same CPLD (MAX II EPM240 CPLD) and I did it as shown in the following VHDL code.

    Code ( (Unknown Language)):
    1. library IEEE;
    2. use IEEE.STD_LOGIC_1164.ALL;
    3. use IEEE.NUMERIC_STD.ALL;
    4.  
    5. entity final is
    6. port(   clk_in_for_fixed,clk_in_for_programmable,xor_in_1,xor_in_2,not1_in1,not2_in2: in std_logic;
    7.         clk_out_fixed, clk_out_programmable,xor_out,not1_out,not2_out: out std_logic;
    8.         programmable_divide_value : in std_logic_vector (9 downto 0)
    9.         );
    10. end final;
    11.  
    12. architecture Behavioral of final is
    13.  
    14. signal counter_fixed,counter_programmable,fixed_divide_value,programmable_divide_value : integer := 0;
    15.  
    16. begin
    17. fixed_divide <= 40;
    18. programmable_divide <= to_integer(unsigned(programmable_divide_value(9 downto 0)));
    19.  
    20. process(clk_in_for_programmable)
    21. begin
    22.  
    23.     if( rising_edge(clk_in_for_fixed) ) then
    24.         if(counter_fixed < fixed_divide/2-1,) then
    25.             counter_fixed <= counter_fixed + 1;
    26.  
    27.              fixed_clk_out <= '0';
    28.         elsif(counter < fixed_divide-1) then
    29.             counter <= counter + 1;
    30.             fixed_clk_out <= '1';
    31.         else
    32.              fixed_clk_out <= '0';
    33.             counter_fixed <= 0;
    34.         end if;
    35.     end if;
    36. end process;
    37.  
    38.  if( rising_edge (clk_in_for_programmable) then
    39.         if(counter_programmable< programmable_divide/2-1) then
    40.             counter_programmable <= counter_programmable+ 1;
    41.              clk_out _programmable<= '0';
    42.         elsif(counter_programmable< programmable_divide-1) then
    43.             counter_programmable <= counter_programmable+ 1;
    44.              clk_out _programmable<= '1';
    45.         else
    46.             clk_out_programmable_<= '0';
    47.             counter_programmable_ <= 0;
    48.         end if;
    49.     end if;
    50.  
    51. end process;  
    52.  
    53. end Behavioral;
    Is this the correct method to run processes in parallel in the same CPLD/FPGA?
     
    Last edited by a moderator: Sep 13, 2012
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    Not really. First of all, behavioral architecture is meant for test benches, not for the actual implementation, you should use RTL instead. Second, you are missing another process declaration after the first end process.

    I think you should try to simulate your code and see if it does compile and if it does what you intended.
     
  3. dumindu89

    Thread Starter Member

    Oct 28, 2010
    113
    0
    What? Does behavioral architecture not applicable for actual implementation?

    All the processes in the code shown above should be run in parallel. So, do I need process declaration after the first end process?

    Compilation was successful. But I didn't simulate it yet.
     
  4. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    All processes are executed in parallel and each process needs its own sensitivity list.
    I am not exatly sure with the behavioral architecture, so just try simulating it and see if it works or not. Also see this http://www.freerangefactory.org/dl/free_range_vhdl.pdf
     
  5. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    You should have seperate "process" statements for your two processes. I doubt your code will compile as you've written it. Actually, there is no problem using two "if" clauses in the same process, but they would need to use the same clock, and the "end process" statement before the 2nd one is an error. Better to make two processes each with it's own sensitivity list. Don't worry about the behavioral thing; modern compilers work just fine with this style.
     
    dumindu89 likes this.
  6. dumindu89

    Thread Starter Member

    Oct 28, 2010
    113
    0
    I modified the code. Are there any thing to be modified further?

    Code ( (Unknown Language)):
    1.  
    2. library IEEE;
    3.  use IEEE.STD_LOGIC_1164.ALL;
    4. use IEEE.NUMERIC_STD.ALL;  
    5. entity final is
    6. port(   clk_in_for_fixed,clk_in_for_programmable,xor_in_1,xor_in_2,not1_in1,not2_in2: in std_logic;        
    7. clk_out_fixed, clk_out_programmable,xor_out,not1_out,not2_out: out std_logic;        
    8. programmable_divide_value : in std_logic_vector (9 downto 0)
    9.         );
    10. end final;  
    11.  
    12. architecture Behavioral of final is  
    13. signal counter_fixed,counter_programmable,fixed_divide_value,programmable_divide_value : integer := 0;
    14.  
    15. begin
    16. fixed_divide <= 40;
    17. programmable_divide <= to_integer(unsigned(programmable_divide_value(9 downto 0)));  
    18.  
    19. process(clk_in_for_fixed)
    20. begin      
    21. if( rising_edge(clk_in_for_fixed) )
    22. then         if(counter_fixed < fixed_divide/2-1,)
    23. then             counter_fixed <= counter_fixed + 1;               fixed_clk_out <= '0';        
    24. elsif(counter < fixed_divide-1) then             counter <= counter + 1;             fixed_clk_out <= '1';        
    25. else              fixed_clk_out <= '0';             counter_fixed <= 0;
    26.         end if;    
    27. end if;
    28. end process;  
    29.  
    30. process(clk_in_for_programmable)
    31. begin  
    32. if( rising_edge (clk_in_for_programmable)
    33. then         if(counter_programmable< programmable_divide/2-1)
    34. then             counter_programmable <= counter_programmable+ 1;              
    35. clk_out _programmable<= '0';         elsif(counter_programmable< programmable_divide-1)
    36. then             counter_programmable <= counter_programmable+ 1;              clk_out _programmable<= '1';
    37. else             clk_out_programmable_<= '0';             counter_programmable_ <= 0;
    38.         end if;
    39. end if;  
    40. end process;    
    41.  
    42. end Behavioral;
    43.  
     
    Last edited by a moderator: Sep 30, 2012
  7. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Using code tags instead of quote tags makes this much easier to read and analyze.
     
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