RS485 multidrop protocol

Discussion in 'Embedded Systems and Microcontrollers' started by shsaga, Nov 11, 2015.

  1. shsaga

    Thread Starter New Member

    Oct 20, 2015
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    I am trying to develop a protocol to be added to boot code to flash the image file onto multiple slaves. Its an enhancement to existing process of 1 master and 1 slave where one master can download image to only one slave and that is a broadcast message.

    All the nodes on the bus have a unique address. One node is the master that is the only node that is able to start communications. All other nodes can't send anything until the master sends a request to them. The messages from the master are a broadcast in the current scenario and the protocol has to be introduced as now, there might be bus contention due to multiple slaves on the same bus.

    The transceiver in use here is ISL83488 and its had two hardware select lines DE Driver output enable and DI driver input. DE is connected across all devices and if one slave pulls it low, all pull it low. DI on the other hand is output by every unit to its right and received as an input from its left. For this line, A high on the left indicates a low on the right of the slave.

    I was thinking on simple "request/response" protocol: the master sends a request(1st image file chunk ) to all slaves as broadcast and based on the state of the hardware lines, get a response. What could be the best ways to approach this problem?
     
  2. John P

    AAC Fanatic!

    Oct 14, 2008
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    Is it possible that you actually intend to use the ISL83483, ISL83485 or ISL83491? The ISL83488 doesn't seem to match what you've talked about, because it has no DE line. The components that have DE may use one ( ISL83483, ISL83485) or two ( ISL83491) wire pairs, and it's not clear which you're planning.
     
  3. shsaga

    Thread Starter New Member

    Oct 20, 2015
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    Sorry for the delay in response. Yes, the concept of DE and DI lines with ISL83488 which i mentioned above is incorrect. The two lines to be used would be GPIO pins one which is connected throughout all targets - detect line (this is an open-collector bussed signal) and another a enable line. Enable signal is outpt by every slave to its right ans input from its left. for a unit with no units to its left input would read asserted.
     
  4. John P

    AAC Fanatic!

    Oct 14, 2008
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    You're still not giving enough information to make any useful comments. How about a circuit diagram of a typical node in the system?
     
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