RS232 testbench

Discussion in 'Embedded Systems and Microcontrollers' started by domino89, May 15, 2014.

  1. domino89

    Thread Starter New Member

    Sep 24, 2013
    22
    0
    I have wierd problem with RS232 implementation it works on board but dunno whats wrong with testbench it just doesnt work. Could somone take a look on this testbench code...
    Code ( (Unknown Language)):
    1. `timescale 1ns
    2.  
    3. module testbench;
    4.  
    5.     // Inputs
    6.     reg RXD_i;
    7.     reg clk_i;
    8.  
    9.     // Outputs
    10.     wire TXD_o;
    11.  
    12.     // Instantiate the Unit Under Test (UUT)
    13.     main uut (
    14.         .RXD_i(RXD_i),
    15.         .clk_i(clk_i),
    16.         .TXD_o(TXD_o)
    17.     );
    18.  
    19.     initial
    20.     begin
    21.         // Initialize Inputs
    22.     clk_i=0;
    23.     RXD_i=1'b1;
    24.  
    25.     #100 RXD_i=0;
    26.     #10 RXD_i=0;
    27.     #10 RXD_i=1;
    28.     #10 RXD_i=0;
    29.     #10 RXD_i=1;
    30.     #10 RXD_i=1;
    31.     #10 RXD_i=1;
    32.     #10 RXD_i=0;
    33.     #10 RXD_i=1;
    34.     #10 RXD_i=0;
    35.         end
    36.  
    37.         always
    38.         #5 clk_i =~clk_i;      
    39. endmodule
    And I get on TxD_o "1" for whole simulation
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    What do you expect to get?
     
  3. domino89

    Thread Starter New Member

    Sep 24, 2013
    22
    0
    It sends what it gets on input.
     
  4. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Since I don't know how the UUT is coded, I cannot verify your expected results. If it use a UART, you need to write something to the TX buffer.
     
  5. domino89

    Thread Starter New Member

    Sep 24, 2013
    22
    0
    This rs232 code which i was testing. This version transmitts what it receives. Parameter N is reduced for testbench purpose. As a said before wierd thing is that it works on board with hyperterminal, but i struggle with this testbench
    Code ( (Unknown Language)):
    1.  
    2. ********************************
    3. *******MAIN MODULE***************
    4. ********************************
    5. `timescale 1ns / 1ps
    6.  
    7. module main (RXD_i, clk_i, TXD_o
    8.     );
    9.  
    10. input RXD_i, clk_i;
    11. output TXD_o;
    12. wire [9:0]receive;
    13.  
    14. receiver A(RXD_i, receive, clk_i, save);
    15. transmitter B(TXD_o, receive, clk_i, save);
    16.  
    17. endmodule
    18.  
    19. ********************************
    20. *******RECEIVER MODULE***********
    21. ********************************
    22.  
    23. `timescale 1ns / 1ps
    24.  
    25. module receiver (RXD_i, receive, clk_i, save);
    26.  
    27. input RXD_i, clk_i;
    28. output reg [9:0]receive, save=0;
    29. integer div1=0, bits_counter1=0, start1=0;
    30. reg [9:0]send;
    31. parameter N = 2; //5208
    32.  
    33. always @(posedge clk_i)
    34. begin
    35. save=0;
    36. if(start1==0)
    37. begin
    38.     receive[0]=1'b1;
    39.     receive[1]=1'b1;
    40.     receive[2]=1'b1;
    41.     receive[3]=1'b1;
    42.     receive[4]=1'b1;
    43.     receive[5]=1'b1;
    44.     receive[6]=1'b1;
    45.     receive[7]=1'b1;
    46.     receive[8]=1'b1;
    47.     receive[9]=1'b1;
    48.     end
    49.    
    50. if(RXD_i==1'b0 && start1==0)
    51. start1=1;
    52.  
    53. if(start1==1)
    54. begin  
    55.     if(div1==N)
    56.     div1=0;
    57.     else if(div1==N/2)
    58.     begin
    59.     div1=div1+1;
    60.     bits_counter1=bits_counter1+1;
    61.     case(bits_counter1)
    62.     0   :   receive[0]=RXD_i;
    63.     1   :   receive[1]=RXD_i;
    64.     2   :   receive[2]=RXD_i;
    65.     3   :   receive[3]=RXD_i;
    66.     4   :   receive[4]=RXD_i;
    67.     5   :   receive[5]=RXD_i;
    68.     6   :   receive[6]=RXD_i;
    69.     7   :   receive[7]=RXD_i;
    70.     8   :   receive[8]=RXD_i;
    71.     9   :   receive[9]=RXD_i;
    72.     endcase
    73.     end
    74.     else
    75.     div1=div1+1;
    76.  
    77.     if(bits_counter1>9)
    78.     begin
    79.     save=1;
    80.     start1=0;
    81.     bits_counter1=0;
    82.     div1=0;
    83.     end
    84.     end
    85.     end
    86. endmodule
    87.  
    88. ********************************
    89. *******TRANSMITTER MODULE********
    90. ********************************
    91.  
    92. `timescale 1ns / 1ps
    93.  
    94. module transmitter (TXD_o, receive, clk_i, save);
    95.      
    96. input [9:0]receive, clk_i, save=0;
    97. output reg TXD_o;
    98. integer div=0, bits=0, start=0;
    99. reg [9:0]send;
    100. parameter N = 2; //5208
    101.  
    102. always @(posedge clk_i)
    103. begin  
    104. if(save==1)
    105. begin
    106. send<=receive;
    107. start=1;
    108. end
    109. if(start==1)
    110. begin
    111.     if(div==N)
    112.         div=0;
    113.     else if(div==N/2)
    114.     begin
    115.     div=div+1;
    116.     bits=bits+1;
    117.         case(bits)
    118.     0   :   TXD_o<=send[0];
    119.     1   :   TXD_o<=send[1];
    120.     2   :   TXD_o<=send[2];
    121.     3   :   TXD_o<=send[3];
    122.     4   :   TXD_o<=send[4];
    123.     5   :   TXD_o<=send[5];
    124.     6   :   TXD_o<=send[6];
    125.     7   :   TXD_o<=send[7];
    126.     8   :   TXD_o<=send[8];
    127.     9   :   TXD_o<=send[9];
    128.     endcase
    129.     end
    130.     else
    131.     div=div+1;
    132.    
    133.     if(bits>9)
    134.     begin
    135.     bits=0;
    136.     start=0;
    137.     div=0;
    138.     end
    139.     end
    140.     else if(start==0)
    141.     TXD_o<=1'b1;
    142.     end
    143. endmodule
    144.  
    145.  
     
    Last edited: May 21, 2014
  6. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    I would start by fixing all the "start1" statements. eg:
    Code ( (Unknown Language)):
    1.  
    2.  
    3.  start1 1=0;
    4.  
    After that, start a wave window and begin looking at waveforms. That's how debug gets done.
     
  7. domino89

    Thread Starter New Member

    Sep 24, 2013
    22
    0
    OH sry i didint notice I have posted version with this bug... Ofc all "start1 1" was replaced with start1.
     
  8. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Look at start1 with a wave viewer and see what it's doing.
     
  9. domino89

    Thread Starter New Member

    Sep 24, 2013
    22
    0
    It works... I had an error in testbench clk declaration (forget that #5 refers to time of low/high time not a period of clock)
     
  10. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Glad you got it to work. You might try something like this for your testbench code in the future:

    Code ( (Unknown Language)):
    1.  
    2.  ....
    3.  
    4.  always
    5.  #5 clk <= ~clk;
    6.  
    7.  initial begin
    8.  wire [0:15] RXD_BUFF = 16'b101010.....;
    9.  integer i = 0;
    10.  end
    11.  
    12.  always @posedge(clk) begin
    13.     if(i<16)
    14.      RXD <= RXD_BUFF[i];
    15.  end
    16.  ....
    17.  [/i]
     
    Last edited: May 21, 2014
  11. domino89

    Thread Starter New Member

    Sep 24, 2013
    22
    0
    Thanks for help
     
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