RS232 Receiver in VHDL

Thread Starter

omerysmi

Joined Oct 10, 2014
55
I want to implement rs232 receiver in vhdl with FPGA Altera DE1.
I have try to write some code but I know that is not good, my main problem is that I dont know how to get an indictaion that new data(serial data) is coming..so actually what I did is to move each bit of the serial data to the out parallel data (8 bits) every rising edge of the main clock

This is the code I have wrriten (again, it's not good of course but I don't know how to continue):

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity receiver is
port(Clock, Reset : in std_logic;
Data_in : in std_logic;
Data_Out : out std_logic_vector(7 downto 0));
end entity;

architecture arc of receiver is
signal index : integer range 0 to 7:=0;
signal inbuffer : std_logic;
begin
process(Clock, Reset)
begin
if Reset='0' then
Data_Out<=(others=>'0');
index<=0;
elsif rising_edge(Clock) then
if(index<8)
inbuffer<=Data_in;
Data_Out(index)<=inbuffer;
index<=index+1;
else
index<=0;
end if;
end if;
end process;
end arc;
 

Brownout

Joined Jan 10, 2012
2,390
Since you're receiving a serial data stream, you need to implement a serial shift register. so, this

inbuffer<=Data_in;


Needs to look something like this:

inbuffer <= inbuffer(7 downto 1) & Data_in;

That's a place to start makeing it 'right'
 

Brownout

Joined Jan 10, 2012
2,390
To get an indication that new data is coming, you monitor the data line for a "space" or "0" condition. To make this work, you'll need a simple state machine with two states: "idle" and "receive" or whichever names suit you. In the "idle" state, this is were you'lll monitor the incoming stream for a 0. Then you'll go to the "receive" state where you'll capture receive data.
 
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