RS flip flop 3 bit Asynchronous counter (urgent)

Discussion in 'Homework Help' started by CSharpque, Dec 15, 2011.

  1. CSharpque

    Thread Starter Member

    Sep 23, 2011
    40
    0
    hello
    can anyone explain how RS flip flop asynchronous counter work from it is diagram.
    i know it count specific event at the time when positive clock plus occur. Ech flip flop have clock signal depend on each flip flop work. But i can't understand from circuit diagram.
    It's urgent . help me
     
  2. JDT

    Well-Known Member

    Feb 12, 2009
    658
    85
    Have you got a circuit diagram? Can you post it?

    Actually, an RS (Reset Set) flip-flop is no good for a counter. You need "master - slave" flip-flops that have a clock input. Usually called "JK" or "D". These are wired to toggle (change state) on the edge of a clock pulse. Connect a number of these in a string so that each flip-flop is clocked by the output of the preceding one, then you have made an asynchronous counter.

    This is called an asynchronous counter because there is always a small delay from the clock edge to the output changing state in every flip-flop. So if there are a number of them in a string then the last one can change state a significant time later.

    In a synchronous counter all the clock inputs are wired together so all the flip-flops change state simultaneously. Logic is used to control which ones actually change state. Important where the output of the counter is decoded by more logic.
     
  3. CSharpque

    Thread Starter Member

    Sep 23, 2011
    40
    0
    Here is the attachment that contain the circuit diagram for RS asynchronous counter
     
  4. Zazoo

    Member

    Jul 27, 2011
    114
    43
    The inverted and non-inverted outputs of the first SR flip-flop (X and X' respectively) are connected back to the the inputs of the same flip-flop (R and S respectively.)
    This connection creates a flip-flop that toggles on each postive edge of the clock - i.e. if the current state is a 1, the flip-flop resets (to 0) on the next postive edge (S=0, R=1). And vice versa.

    The inverted output of each flip-flop (X') acts as the clock for the next flip-flop. Since this output is toggling, the same processes occurs for each later stage, but at half the frequency of the previous stage (with the first stage being triggered externally.)
     
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