Please help me analyse this circuits. Here's my reasoning; for the positive half cycle, D2 is on and D1 if off. As current flows, the Inductor is energized, as Vs goes to 0( negative half cycle, then D2 is off, D1 is on. At the point D1 is on, the inductor sends current through D1 untill it's fully depleted. During that depletion stage, i assumed that the voltage would start out being as high as Vs but it seems not. Could you please explain what's happening and what causes the oscillation between the rectified cycles?

 

If this is the sample of how you plan to present information in your lab reports, then I expect you to fail.

 

Thanks Shteii01.

Let me give you example.
I don't use LTspice. When I went to Purdue we used MultiSim. So I am looking at SINE(0 12 60) and I ask myself what kind of sinusoidal signal is it? What amplitude? What frequency?

Whose responsibility it is to present information in clear and organized manner? Mine? Or the person's who wants my help?
If you can not or will not invest time and effort to present your information in clear and organized manner, well, then I will not spend my time on it either. It really is that simple.

 

Let me give you example.
I don't use LTspice. When I went to Purdue we used MultiSim. So I am looking at SINE(0 12 60) and I ask myself what kind of sinusoidal signal is it? What amplitude? What frequency?

Whose responsibility it is to present information in clear and organized manner? Mine? Or the person's who wants my help?
If you can not or will not invest time and effort to present your information in clear and organized manner, well, then I will not spend my time on it either. It really is that simple.

Take it easy Sheii01, My entire text didn't paste. In any case, I assume LT spice is widely used. SINE(0 12 60) would be amplitude of 12 and frequency of 60)