Ripple counter race condition

Discussion in 'The Projects Forum' started by citizencoolguy, Mar 17, 2011.

  1. citizencoolguy

    Thread Starter New Member

    Jan 17, 2011
    12
    0
    Hello,

    I'm using a binary ripple counter with the clock input signal and the divide by 64 signal (from the counter) running into an AND gate. The problem is that because it's a ripple counter the propogation delay for the divide by 64 signal adds up to about 150ns, thus causing a race condition at the and gate. I was wonder if there are any cheap simple ways to correct this. I could use a Low pass filter to delay the signal a little,but i want to procuce a few of these and the duty cycle on each will by slightly different because of the variance in the switching threshold on the gates. I've also messed around with all pass filters a little, but havent had much success.
    Thanks
     
  2. guitarguy12387

    Active Member

    Apr 10, 2008
    359
    12
    Why not use a carry lookahead adder?
     
  3. Bernard

    AAC Fanatic!

    Aug 7, 2008
    4,176
    397
    What is clock rate & duty cycle ? Where does output from AND go?
     
  4. Wendy

    Moderator

    Mar 24, 2008
    20,766
    2,536
    Are you trying to limit the count with the AND gate? That is the only way I see propagation makes a difference.
     
  5. eblc1388

    Senior Member

    Nov 28, 2008
    1,542
    102
    Yes.

    Decode state 63 and then sync the change at the edge of the 64th clock pulse, using a F/F.
     
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