Ripple Counter Design Problem

Discussion in 'Homework Help' started by BlayneA, Feb 15, 2016.

  1. BlayneA

    Thread Starter New Member

    Oct 27, 2015
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    I am required to build a "dice game" using my choice of the 7490, 7492, or 7493 ripple counters as the basis of my circuit. The way the circuit must work is as follows: A pushbutton must be pressed and released to simulate the roll of the die. While the switch is held down, a numerical 8 is displayed, and when the button is released a random value between 1 and 6 should appear on the 7-segment display. I also need to supply my own debounced pushbutton (my switch in the screenshot provided represents this.)

    My circuit works perfectly fine (in Multisim atleast) other than the fact that my clock counts from 0-6 and then repeats, rather than the required 1 through 6 that simulates actual dice values. I have the circuit set up so that instead of going through its normal 3-bit count of 0-7, the three outputs of the counter are ANDed together and sent to the RESET inputs of the counter to indicate its invalid state and reset it early. Other notes to make is that one of the rules is only a +5V power supply is given, so I had to make an oscillator using the 555 Timer, which is why its there rather than a function generator. I also obviously used the 7492 but only used three of the flip flops since I only need a maximum of 6 states, but it gives me 8 states and I have only eliminated one of the two invalid states (7) and have yet to remove the other (0.)

    I have spent hours thinking of how to fix my issue. In addition to the option of my actual circuit design not being possible to achieve the conditions that I wish to achieve, I have tried decoding the outputs of the clock by adding logic gates based off of a truth table that I constructed to remove the possibility of displaying a 0, but then I get something like a constant 1 being displayed when the switch is closed/open. I've looked at the 74LS47 decoder/driver datasheet to see what values actually allow a zero to be displayed, which is obviously all of the inputs to the decoder low, so I imagine (if my circuit is capable of this) that I somehow need to prevent the inputs from ever all reaching zero, or have the 7-segment display display another value between one and six for that one unique state where all three of the clock outputs go low (0.) My best guess at preventing all the outputs from reaching zero is to reform the counter into a DOWN counter, and making 000 the false state, and resetting at 1 instead, but then a 7 will be displayed again. I feel like the answer is right in front of me but I can't wrap my head around it.
     
  2. BlayneA

    Thread Starter New Member

    Oct 27, 2015
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    Having troubles getting my image to attach, my apologies...trying to fix it now for anyone that views this.
     
  3. WBahn

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    Mar 31, 2012
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    As with most things, there are multiple ways to tackle the problem. How would you "reform" one of the three counters you described into a down counter?

    If you have a counter that outputs values 0 to 5, how hard would it be to follow that 3-bit value with an adder that adds 1 to it?
     
  4. BlayneA

    Thread Starter New Member

    Oct 27, 2015
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  5. BlayneA

    Thread Starter New Member

    Oct 27, 2015
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    To make a down counter the Q' outputs of each flip flop are tied to the clock input of each successive flip-flop rather than the Q ouputs, so with the IC that I chose I suppose it is impossible after looking at the pin diagram and gate level diagram of the chip. But as for your question, I don't really understand what you mean by an adder that "adds" one TO the 3-bit output? I am aware of a full adder that could add the three bits together by A B and Carry-in Inputs to achieve a sum of those inputs, though.
     
  6. BlayneA

    Thread Starter New Member

    Oct 27, 2015
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    I take back the first thing that I said, if I invert the A output that is tied to the Clock B input on the counter, then it turns to a down counter but now only counts down from 5, so now what you said makes more sense, and I will get back to you on if I succeed or not
     
  7. WBahn

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    Mar 31, 2012
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    It sounds like you are designing via happening -- meaning that you are making seemingly random changes to the circuit and then hoping that, at some point, it will happen to work the way you want it to.

    Do you know how to take three full adders and make a 3-bit adder? If so, look at the simplifications you can make if one input is the output of your counter, the other input is 001, and the carry-in input is LO. What you'll see is that you can implement this special-case adder using just three half-adders. In fact, you don't need the carry-out logic of the last adder stage.
     
  8. BlayneA

    Thread Starter New Member

    Oct 27, 2015
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    You are exactly right about the random changes thing. I had a systematic approach until I realized that my circuit showed a 0, and from there it was just me throwing things at the circuit, somewhat logically, mostly not, hoping it would work.

    Just got it to work the way I needed it to, only thing is I used the 4-bit adder IC to simplify things, adding the three outputs to a binary 1 to shift all of the inputs up. Crazy how this seems so obvious to me now. In regards to the three half adders, I don't really follow completely because you said that you don't need the carry-out logic of the LAST adders stage, but since each half adder only has two inputs (which are all being taken up by the counter and the binary 1) where do the two "used" carry outputs of the first two stages go?
     
  9. WBahn

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    Mar 31, 2012
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    First, sketch a schematic of a 3-bit adder using full adders. That will give us a common starting point for a discussion.
     
  10. BlayneA

    Thread Starter New Member

    Oct 27, 2015
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    Wasn't sure if you wanted a simple block diagram or the full deal.

    As for the labels, from the top adder to the bottom, A0 is the LSB of the counter, B1 is the 1 (LSB) of the 001 that's being added to the counter, A1 of the second adder is the ones place of the counter, B0 is the ones place of the 001 being added, A2 of the third adder is the MSB of the counter output, B0 is the MSB of the 001 output. The initial carry input of the first adder is LOW, and each carry output of the first two adders is tied to the next successive counters Carry-In input.

    As for the simplification process, I imagine that you then concluded that you can just tie the carry-out outputs of the half adders into the second operand of each half adder to eliminate finding an external high/low source to go into those inputs? (The B inputs of the half adders that is, the A inputs being the counter)
     
  11. WBahn

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    Mar 31, 2012
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    The contrast on your image is pretty poor, but I can (barely) make out enough to work with.

    I think you have the basic idea for the simplification process, though what it really amounts to is examining the implications of each input that is at a fixed value. For instance, if I have an AND gate that has one dynamic input (an input whose value is NOT fixed) and the other input is always HI, then the output will always be the same as the dynamic input and I can eliminate the AND gate. If that other input is always LO, then the output will always be LO and, again, I can eliminate the AND gate.

    So go through that process and you will see that you can eliminate a very significant number of the gates.
     
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