Revision help!

Discussion in 'Homework Help' started by cps13, May 13, 2014.

  1. cps13

    Thread Starter New Member

    Feb 25, 2013
    9
    0
    Hi guys,

    I have an exam coming up for my HNC electronics. I am ok with all of the topics apart from flip flops. I just cannot understand them.

    I have attached an example from a mock paper of what I need to do - the answer is shown on it to prove that i'm not trying to cheat. The problem is, even with the answer I just don't get it.

    Can anyone shed some light on the topic, or suggest some good reading for it.

    I have looked at the truth tables for JKs. I think my main questions are:

    What are the outputs when a JK is set or reset to start with?

    On the circuit diagram on the question the reset input is shown as 1. Does this mean that the JK is reset in between every clock input?

    Thanks
     
  2. Hop

    New Member

    Feb 14, 2013
    4
    0
    The Q output of the JK will be logic 1 when the SET input is active (high). The not-Q output of the JK will be logic 1 when the RESET input is active (high). If both SET and RESET are active, the output depends on how the JK is implemented as it is possible that both the Q and the not-Q outputs could be at logic 1. Assuming that SET and RESET are not both asserted at the same time, the Q output is complimentary to the not-Q output.

    The SET and RESET inputs are asynchronous and when asserted override any activity on the CLOCK input. There are minimum set-up time requirements between the removal of SET or RESET assertion and the next low-to-high transition of the CLOCK input that would result in a change of state of the JK. Refer to manufacturer's data sheet.

    To answer your last question: Yes, the JK is reset in between every clock input. More specifically, it is reset regardless of the clock input. In other words the clock input is ignored while the reset is active.

    The diagram shows Reset being active, and RESET on both JKs being active, until Reset is made inactive about three quarters of the way into the first clock cycle. The SET input on both JKs is always inactive. This means neither JK will toggle until Reset is made inactive. Both JK Q-outputs remain at logic 0, and their not-Q outputs remain at logic 1, until Reset is made inactive and the rising edge of the CLOCK occurs. Note there is always a minimum "set-up" time interval between the two events: Reset inactive and rising edge of Clock.
     
  3. Papabravo

    Expert

    Feb 24, 2006
    10,135
    1,786
    To simplify your thinking.

    With 2 inputs, J and K, there are four possible things for the device to do:
    Set the output to 1, regardless of current state.
    Set the output to 0, regardless of current state.
    Hold the present output by doing nothing at all.
    Complement the present output.​

    The only case in which the present output is relevant is the last case.
    Last point -- everything happens on the clock edge. As long as J and K meet the setup time requirements they can behave in an arbitrary fashion between clock edges.
     
    Last edited: May 13, 2014
  4. cps13

    Thread Starter New Member

    Feb 25, 2013
    9
    0
    Thanks for your help.

    Please can you explain what you mean by the below?

     
  5. Papabravo

    Expert

    Feb 24, 2006
    10,135
    1,786
    Sure. It is a requirement of all synchronous circuits, including flip-flops, counters, shift registers and so forth, that the inputs such as J and K be stable for some period of time prior to the clock edge. Typical setup times are in the range of a few nanoseconds to maybe 20 nanoseconds. Violation of setup time requirements can result in metastability.

    http://en.wikipedia.org/wiki/Metastability
    http://en.wikipedia.org/wiki/Metastability_in_electronics
    http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/tsu_and_th.pdf

    They also have hold time requirements where the inputs cannot change for a certain period after the clock edge. Hold times are typically shorter on the order of 0 to 5 nanoseconds.
     
  6. WBahn

    Moderator

    Mar 31, 2012
    17,715
    4,788
    I would think that the present output is relevant to the next-to-last case, as well.
     
  7. Papabravo

    Expert

    Feb 24, 2006
    10,135
    1,786
    Maybe, but that case is also equivalent to ignoring the clock which does not depend on the current state. I guess it depends on how the function is implemented internally.
     
Loading...